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s-barannikovs-barannikov
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Try to get the naming right
1 parent e3725dd commit 776a241

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7 files changed

+36
-39
lines changed

7 files changed

+36
-39
lines changed

‎llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2590,14 +2590,14 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
25902590
return true;
25912591
}
25922592

2593-
case ARM::MOVsrl_glue:
2594-
case ARM::MOVsra_glue: {
2593+
case ARM::LSRs1:
2594+
case ARM::ASRs1: {
25952595
// These are just fancy MOVs instructions.
25962596
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
25972597
MI.getOperand(0).getReg())
25982598
.add(MI.getOperand(1))
25992599
.addImm(ARM_AM::getSORegOpc(
2600-
(Opcode == ARM::MOVsrl_glue ? ARM_AM::lsr : ARM_AM::asr), 1))
2600+
(Opcode == ARM::LSRs1 ? ARM_AM::lsr : ARM_AM::asr), 1))
26012601
.add(predOps(ARMCC::AL))
26022602
.addReg(ARM::CPSR, RegState::Define);
26032603
MI.eraseFromParent();

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1733,14 +1733,14 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
17331733
MAKE_CASE(ARMISD::ASRL)
17341734
MAKE_CASE(ARMISD::LSRL)
17351735
MAKE_CASE(ARMISD::LSLL)
1736-
MAKE_CASE(ARMISD::SRL_GLUE)
1737-
MAKE_CASE(ARMISD::SRA_GLUE)
1736+
MAKE_CASE(ARMISD::LSLS)
1737+
MAKE_CASE(ARMISD::LSRS1)
1738+
MAKE_CASE(ARMISD::ASRS1)
17381739
MAKE_CASE(ARMISD::RRX)
17391740
MAKE_CASE(ARMISD::ADDC)
17401741
MAKE_CASE(ARMISD::ADDE)
17411742
MAKE_CASE(ARMISD::SUBC)
17421743
MAKE_CASE(ARMISD::SUBE)
1743-
MAKE_CASE(ARMISD::LSLS)
17441744
MAKE_CASE(ARMISD::VMOVRRD)
17451745
MAKE_CASE(ARMISD::VMOVDRR)
17461746
MAKE_CASE(ARMISD::VMOVhr)
@@ -6850,9 +6850,9 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
68506850
SDValue Lo, Hi;
68516851
std::tie(Lo, Hi) = DAG.SplitScalar(N->getOperand(0), dl, MVT::i32, MVT::i32);
68526852

6853-
// First, build a SRA_GLUE/SRL_GLUE op, which shifts the top part by one and
6854-
// captures the result into a carry flag.
6855-
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_GLUE:ARMISD::SRA_GLUE;
6853+
// First, build a LSRS1/ASRS1 op, which shifts the top part by one and
6854+
// captures the shifted out bit into a carry flag.
6855+
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::LSRS1 : ARMISD::ASRS1;
68566856
Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, FlagsVT), Hi);
68576857

68586858
// The low part is an ARMISD::RRX operand, which shifts the carry in.

‎llvm/lib/Target/ARM/ARMISelLowering.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -101,15 +101,15 @@ class VectorType;
101101

102102
BCC_i64,
103103

104-
SRL_GLUE, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
105-
SRA_GLUE, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
106-
RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
104+
LSLS, // Flag-setting shift left.
105+
LSRS1, // Flag-setting logical shift right by one bit.
106+
ASRS1, // Flag-setting arithmetic shift right by one bit.
107+
RRX, // Flag-setting shift right one bit with carry in.
107108

108109
ADDC, // Add with carry
109110
ADDE, // Add using carry
110111
SUBC, // Sub with carry
111112
SUBE, // Sub using carry
112-
LSLS, // Shift left producing carry
113113

114114
VMOVRRD, // double to two gprs.
115115
VMOVDRR, // Two gprs to double.

‎llvm/lib/Target/ARM/ARMInstrInfo.td‎

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -206,9 +206,9 @@ def ARMasrl : SDNode<"ARMISD::ASRL", SDT_ARMIntShiftParts, []>;
206206
def ARMlsrl : SDNode<"ARMISD::LSRL", SDT_ARMIntShiftParts, []>;
207207
def ARMlsll : SDNode<"ARMISD::LSLL", SDT_ARMIntShiftParts, []>;
208208

209-
def ARMsrl_glue : SDNode<"ARMISD::SRL_GLUE", SDTIntUnaryOpWithFlagsOut>;
210-
def ARMsra_glue : SDNode<"ARMISD::SRA_GLUE", SDTIntUnaryOpWithFlagsOut>;
211-
def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOpWithFlagsIn>;
209+
def ARMlsrs1 : SDNode<"ARMISD::LSRS1", SDTIntUnaryOpWithFlagsOut>;
210+
def ARMasrs1 : SDNode<"ARMISD::ASRS1", SDTIntUnaryOpWithFlagsOut>;
211+
def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOpWithFlagsIn>;
212212

213213
def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
214214
[SDNPCommutative]>;
@@ -3745,20 +3745,17 @@ def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
37453745
Requires<[IsARM, HasV6T2]>;
37463746

37473747
let Uses = [CPSR] in
3748-
def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3749-
[(set GPR:$Rd, (ARMrrx GPR:$Rm, CPSR))]>,
3750-
UnaryDP, Requires<[IsARM]>, Sched<[WriteALU]>;
3751-
3752-
// These aren't really mov instructions, but we have to define them this way
3753-
// due to glue operands.
3748+
def RRX : PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3749+
[(set GPR:$Rd, (ARMrrx GPR:$Rm, CPSR))]>,
3750+
UnaryDP, Requires<[IsARM]>, Sched<[WriteALU]>;
37543751

37553752
let Defs = [CPSR] in {
3756-
def MOVsrl_glue : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3757-
[(set GPR:$dst, CPSR, (ARMsrl_glue GPR:$src))]>,
3758-
UnaryDP, Sched<[WriteALU]>, Requires<[IsARM]>;
3759-
def MOVsra_glue : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3760-
[(set GPR:$dst, CPSR, (ARMsra_glue GPR:$src))]>,
3761-
UnaryDP, Sched<[WriteALU]>, Requires<[IsARM]>;
3753+
def LSRs1 : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3754+
[(set GPR:$dst, CPSR, (ARMlsrs1 GPR:$src))]>,
3755+
UnaryDP, Sched<[WriteALU]>, Requires<[IsARM]>;
3756+
def ASRs1 : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3757+
[(set GPR:$dst, CPSR, (ARMasrs1 GPR:$src))]>,
3758+
UnaryDP, Sched<[WriteALU]>, Requires<[IsARM]>;
37623759
}
37633760

37643761
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/ARM/ARMInstrThumb2.td‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2801,11 +2801,12 @@ def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
28012801
}
28022802
}
28032803

2804+
// These differ from t2LSRri / t2ASRri in that they are flag-setting
2805+
// and have a hardcoded shift amount = 1.
28042806
let isCodeGenOnly = 1, Defs = [CPSR] in {
2805-
def t2MOVsrl_glue
2806-
: T2TwoRegShiftImm<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2807-
"lsrs", ".w\t$Rd, $Rm, #1",
2808-
[(set rGPR:$Rd, CPSR, (ARMsrl_glue rGPR:$Rm))]>,
2807+
def t2LSRs1 : T2TwoRegShiftImm<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2808+
"lsrs", ".w\t$Rd, $Rm, #1",
2809+
[(set rGPR:$Rd, CPSR, (ARMlsrs1 rGPR:$Rm))]>,
28092810
Sched<[WriteALU]> {
28102811
let Inst{31-27} = 0b11101;
28112812
let Inst{26-25} = 0b01;
@@ -2817,10 +2818,9 @@ def t2MOVsrl_glue
28172818
let Inst{14-12} = 0b000;
28182819
let Inst{7-6} = 0b01;
28192820
}
2820-
def t2MOVsra_glue
2821-
: T2TwoRegShiftImm<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2822-
"asrs", ".w\t$Rd, $Rm, #1",
2823-
[(set rGPR:$Rd, CPSR, (ARMsra_glue rGPR:$Rm))]>,
2821+
def t2ASRs1 : T2TwoRegShiftImm<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2822+
"asrs", ".w\t$Rd, $Rm, #1",
2823+
[(set rGPR:$Rd, CPSR, (ARMasrs1 rGPR:$Rm))]>,
28242824
Sched<[WriteALU]> {
28252825
let Inst{31-27} = 0b11101;
28262826
let Inst{26-25} = 0b01;

‎llvm/lib/Target/ARM/ARMScheduleM7.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -325,7 +325,7 @@ def M7Ex1ReadNoFastBypass : SchedReadAdvance<-1, [WriteLd, M7LoadLatency1]>;
325325
def : InstRW<[WriteALUsi, M7Ex1ReadNoFastBypass, M7Read_ISS],
326326
(instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
327327
"t2(SUB|CMP|CMNz|TEQ|TST)rs$",
328-
"t2MOVsr(a|l)")>;
328+
"t2(A|L)SRs1")>;
329329
def : InstRW<[WriteALUsi, M7Read_ISS],
330330
(instregex "t2MVNs")>;
331331

@@ -335,7 +335,7 @@ def : InstRW<[WriteALUsi, M7Read_ISS],
335335
// but the results prove to be better than trying to get them exact.
336336

337337
def : InstRW<[M7WriteShift2, M7Read_ISS], (instregex "t2RRX$")>;
338-
def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
338+
def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)r")>;
339339

340340
// Instructions that use the shifter, but have normal timing.
341341

‎llvm/lib/Target/ARM/ARMScheduleM85.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -436,7 +436,7 @@ def : InstRW<[M85WriteALUsi, M85ReadALUsi],
436436
def : InstRW<[M85WriteShift2],
437437
(instregex "t2RRX$")>;
438438
def : InstRW<[WriteALU],
439-
(instregex "(t|t2)(LSL|LSR|ASR|ROR|SBFX|UBFX)", "t2MOVsr(a|l)")>;
439+
(instregex "(t|t2)(LSL|LSR|ASR|ROR|SBFX|UBFX)")>;
440440

441441
// Instructions that use the shifter, but have normal timing
442442

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