[RISCV] Correct the rounding mode for llvm.lround.i64.f32 with RV64+Zfinx.

topperc · topperc · commit 776aef1a5ac7 · 2024-09-01T13:26:38.000-07:00
We should use RMM instead of DYN.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -799,8 +799,8 @@ def : Pat<(i64 (any_lrint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, FRM_DYN)>;
 def : Pat<(i64 (any_llrint FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, FRM_DYN)>;
 
 // float->int64 rounded to neartest with ties rounded away from zero.
-def : Pat<(i64 (any_lround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, FRM_DYN)>;
-def : Pat<(i64 (any_llround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, FRM_DYN)>;
+def : Pat<(i64 (any_lround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, FRM_RMM)>;
+def : Pat<(i64 (any_llround FPR32INX:$rs1)), (FCVT_L_S_INX $rs1, FRM_RMM)>;
 
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W_INX $rs1, FRM_DYN)>;
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
@@ -1473,7 +1473,7 @@ define iXLen @lround_f32(float %a) nounwind strictfp {
 ;
 ; RV64IZFINX-LABEL: lround_f32:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
 ; RV64IZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: lround_f32:
@@ -1577,7 +1577,7 @@ define i64 @llround_f32(float %a) nounwind strictfp {
 ;
 ; RV64IZFINX-LABEL: llround_f32:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
 ; RV64IZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: llround_f32:
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll
@@ -1445,7 +1445,7 @@ define iXLen @lround_f32(float %a) nounwind {
 ;
 ; RV64IZFINX-LABEL: lround_f32:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
 ; RV64IZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: lround_f32:
@@ -1593,7 +1593,7 @@ define i64 @llround_f32(float %a) nounwind {
 ;
 ; RV64IZFINX-LABEL: llround_f32:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    fcvt.l.s a0, a0
+; RV64IZFINX-NEXT:    fcvt.l.s a0, a0, rmm
 ; RV64IZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: llround_f32:

Original file line number	Diff line number	Diff line change
`@@ -1473,7 +1473,7 @@ define iXLen @lround_f32(float %a) nounwind strictfp {`
`1473`	`1473`	`;`
`1474`	`1474`	`; RV64IZFINX-LABEL: lround_f32:`
`1475`	`1475`	`; RV64IZFINX: # %bb.0:`
`1476`		`-; RV64IZFINX-NEXT: fcvt.l.s a0, a0`
	`1476`	`+; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm`
`1477`	`1477`	`; RV64IZFINX-NEXT: ret`
`1478`	`1478`	`;`
`1479`	`1479`	`; RV32I-LABEL: lround_f32:`
`@@ -1577,7 +1577,7 @@ define i64 @llround_f32(float %a) nounwind strictfp {`
`1577`	`1577`	`;`
`1578`	`1578`	`; RV64IZFINX-LABEL: llround_f32:`
`1579`	`1579`	`; RV64IZFINX: # %bb.0:`
`1580`		`-; RV64IZFINX-NEXT: fcvt.l.s a0, a0`
	`1580`	`+; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm`
`1581`	`1581`	`; RV64IZFINX-NEXT: ret`
`1582`	`1582`	`;`
`1583`	`1583`	`; RV32I-LABEL: llround_f32:`
Original file line number	Diff line number	Diff line change
`@@ -1445,7 +1445,7 @@ define iXLen @lround_f32(float %a) nounwind {`
`1445`	`1445`	`;`
`1446`	`1446`	`; RV64IZFINX-LABEL: lround_f32:`
`1447`	`1447`	`; RV64IZFINX: # %bb.0:`
`1448`		`-; RV64IZFINX-NEXT: fcvt.l.s a0, a0`
	`1448`	`+; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm`
`1449`	`1449`	`; RV64IZFINX-NEXT: ret`
`1450`	`1450`	`;`
`1451`	`1451`	`; RV32I-LABEL: lround_f32:`
`@@ -1593,7 +1593,7 @@ define i64 @llround_f32(float %a) nounwind {`
`1593`	`1593`	`;`
`1594`	`1594`	`; RV64IZFINX-LABEL: llround_f32:`
`1595`	`1595`	`; RV64IZFINX: # %bb.0:`
`1596`		`-; RV64IZFINX-NEXT: fcvt.l.s a0, a0`
	`1596`	`+; RV64IZFINX-NEXT: fcvt.l.s a0, a0, rmm`
`1597`	`1597`	`; RV64IZFINX-NEXT: ret`
`1598`	`1598`	`;`
`1599`	`1599`	`; RV32I-LABEL: llround_f32:`