VT/test: add no-nsw-nuw variants of incr tests

Author: artagnon

llvm/test/Analysis/ValueTracking/implied-condition-samesign.ll

@@ -17,6 +17,22 @@ define i1 @incr_sle(i32 %i, i32 %len) {
   ret i1 %res
 }
 
+define i1 @incr_sle_no_nsw_nuw(i32 %i, i32 %len) {
+; CHECK-LABEL: define i1 @incr_sle_no_nsw_nuw(
+; CHECK-SAME: i32 [[I:%.*]], i32 [[LEN:%.*]]) {
+; CHECK-NEXT:    [[I_INCR:%.*]] = add i32 [[I]], 1
+; CHECK-NEXT:    [[I_GT_LEN:%.*]] = icmp samesign ugt i32 [[I]], [[LEN]]
+; CHECK-NEXT:    [[I_INCR_SGT_LEN:%.*]] = icmp sgt i32 [[I_INCR]], [[LEN]]
+; CHECK-NEXT:    [[RES:%.*]] = icmp sle i1 [[I_INCR_SGT_LEN]], [[I_GT_LEN]]
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %i.incr = add i32 %i, 1
+  %i.gt.len = icmp samesign ugt i32 %i, %len
+  %i.incr.sgt.len = icmp sgt i32 %i.incr, %len
+  %res = icmp sle i1 %i.incr.sgt.len, %i.gt.len
+  ret i1 %res
+}
+
 define i1 @incr_sge(i32 %i, i32 %len) {
 ; CHECK-LABEL: define i1 @incr_sge(
 ; CHECK-SAME: i32 [[I:%.*]], i32 [[LEN:%.*]]) {
@@ -33,6 +49,22 @@ define i1 @incr_sge(i32 %i, i32 %len) {
   ret i1 %res
 }
 
+define i1 @incr_sge_no_nsw_nuw(i32 %i, i32 %len) {
+; CHECK-LABEL: define i1 @incr_sge_no_nsw_nuw(
+; CHECK-SAME: i32 [[I:%.*]], i32 [[LEN:%.*]]) {
+; CHECK-NEXT:    [[I_INCR:%.*]] = add i32 [[I]], 1
+; CHECK-NEXT:    [[I_LT_LEN:%.*]] = icmp samesign ult i32 [[I]], [[LEN]]
+; CHECK-NEXT:    [[I_INCR_SLT_LEN:%.*]] = icmp slt i32 [[I_INCR]], [[LEN]]
+; CHECK-NEXT:    [[RES:%.*]] = icmp sge i1 [[I_INCR_SLT_LEN]], [[I_LT_LEN]]
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %i.incr = add i32 %i, 1
+  %i.lt.len = icmp samesign ult i32 %i, %len
+  %i.incr.slt.len = icmp slt i32 %i.incr, %len
+  %res = icmp sge i1 %i.incr.slt.len, %i.lt.len
+  ret i1 %res
+}
+
 define i1 @incr_ule(i32 %i, i32 %len) {
 ; CHECK-LABEL: define i1 @incr_ule(
 ; CHECK-SAME: i32 [[I:%.*]], i32 [[LEN:%.*]]) {
@@ -49,6 +81,22 @@ define i1 @incr_ule(i32 %i, i32 %len) {
   ret i1 %res
 }
 
+define i1 @incr_ule_no_nsw_nuw(i32 %i, i32 %len) {
+; CHECK-LABEL: define i1 @incr_ule_no_nsw_nuw(
+; CHECK-SAME: i32 [[I:%.*]], i32 [[LEN:%.*]]) {
+; CHECK-NEXT:    [[I_INCR:%.*]] = add i32 [[I]], 1
+; CHECK-NEXT:    [[I_GT_LEN:%.*]] = icmp samesign ugt i32 [[I]], [[LEN]]
+; CHECK-NEXT:    [[I_INCR_SGT_LEN:%.*]] = icmp sgt i32 [[I_INCR]], [[LEN]]
+; CHECK-NEXT:    [[RES:%.*]] = icmp ule i1 [[I_GT_LEN]], [[I_INCR_SGT_LEN]]
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %i.incr = add i32 %i, 1
+  %i.gt.len = icmp samesign ugt i32 %i, %len
+  %i.incr.sgt.len = icmp sgt i32 %i.incr, %len
+  %res = icmp ule i1 %i.gt.len, %i.incr.sgt.len
+  ret i1 %res
+}
+
 define i1 @incr_uge(i32 %i, i32 %len) {
 ; CHECK-LABEL: define i1 @incr_uge(
 ; CHECK-SAME: i32 [[I:%.*]], i32 [[LEN:%.*]]) {
@@ -65,6 +113,22 @@ define i1 @incr_uge(i32 %i, i32 %len) {
   ret i1 %res
 }
 
+define i1 @incr_uge_no_nsw_nuw(i32 %i, i32 %len) {
+; CHECK-LABEL: define i1 @incr_uge_no_nsw_nuw(
+; CHECK-SAME: i32 [[I:%.*]], i32 [[LEN:%.*]]) {
+; CHECK-NEXT:    [[I_INCR:%.*]] = add i32 [[I]], 1
+; CHECK-NEXT:    [[I_LT_LEN:%.*]] = icmp samesign ult i32 [[I]], [[LEN]]
+; CHECK-NEXT:    [[I_INCR_SLT_LEN:%.*]] = icmp slt i32 [[I_INCR]], [[LEN]]
+; CHECK-NEXT:    [[RES:%.*]] = icmp uge i1 [[I_LT_LEN]], [[I_INCR_SLT_LEN]]
+; CHECK-NEXT:    ret i1 [[RES]]
+;
+  %i.incr = add i32 %i, 1
+  %i.lt.len = icmp samesign ult i32 %i, %len
+  %i.incr.slt.len = icmp slt i32 %i.incr, %len
+  %res = icmp uge i1 %i.lt.len, %i.incr.slt.len
+  ret i1 %res
+}
+
 define i1 @sgt_implies_ge_via_assume(i32 %i, i32 %j) {
 ; CHECK-LABEL: define i1 @sgt_implies_ge_via_assume(
 ; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]]) {