@@ -257,8 +257,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
257257 bool selectSpvThreadId (Register ResVReg, const SPIRVType *ResType,
258258 MachineInstr &I) const ;
259259
260- bool selectWaveNOpInst (Register ResVReg, const SPIRVType *ResType,
261- MachineInstr &I, unsigned Opcode) const ;
260+ bool selectWaveOpInst (Register ResVReg, const SPIRVType *ResType,
261+ MachineInstr &I, unsigned Opcode) const ;
262262
263263 bool selectWaveActiveCountBits (Register ResVReg, const SPIRVType *ResType,
264264 MachineInstr &I) const ;
@@ -1949,10 +1949,10 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
19491949 return Result;
19501950}
19511951
1952- bool SPIRVInstructionSelector::selectWaveNOpInst (Register ResVReg,
1953- const SPIRVType *ResType,
1954- MachineInstr &I,
1955- unsigned Opcode) const {
1952+ bool SPIRVInstructionSelector::selectWaveOpInst (Register ResVReg,
1953+ const SPIRVType *ResType,
1954+ MachineInstr &I,
1955+ unsigned Opcode) const {
19561956 MachineBasicBlock &BB = *I.getParent ();
19571957 SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType (32 , I, TII);
19581958
@@ -1975,8 +1975,8 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
19751975 SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType (32 , I, TII);
19761976 SPIRVType *BallotType = GR.getOrCreateSPIRVVectorType (IntTy, 4 , I, TII);
19771977 Register BallotReg = MRI->createVirtualRegister (GR.getRegClass (BallotType));
1978- bool Result = selectWaveNOpInst (BallotReg, BallotType, I,
1979- SPIRV::OpGroupNonUniformBallot);
1978+ bool Result = selectWaveOpInst (BallotReg, BallotType, I,
1979+ SPIRV::OpGroupNonUniformBallot);
19801980
19811981 MachineBasicBlock &BB = *I.getParent ();
19821982 Result &=
@@ -2819,13 +2819,12 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
28192819 case Intrinsic::spv_wave_active_countbits:
28202820 return selectWaveActiveCountBits (ResVReg, ResType, I);
28212821 case Intrinsic::spv_wave_any:
2822- return selectWaveNOpInst (ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
2822+ return selectWaveOpInst (ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
28232823 case Intrinsic::spv_wave_is_first_lane:
2824- return selectWaveNOpInst (ResVReg, ResType, I,
2825- SPIRV::OpGroupNonUniformElect);
2824+ return selectWaveOpInst (ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect);
28262825 case Intrinsic::spv_wave_readlane:
2827- return selectWaveNOpInst (ResVReg, ResType, I,
2828- SPIRV::OpGroupNonUniformShuffle);
2826+ return selectWaveOpInst (ResVReg, ResType, I,
2827+ SPIRV::OpGroupNonUniformShuffle);
28292828 case Intrinsic::spv_step:
28302829 return selectExtInst (ResVReg, ResType, I, CL::step, GL::Step);
28312830 case Intrinsic::spv_radians:
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