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9 files changed

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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -831,8 +831,9 @@ static bool relaxableFixupNeedsRelocation(const MCFixupKind Kind) {
831831
default:
832832
break;
833833
case RISCV::fixup_riscv_rvc_jump:
834+
case RISCV::fixup_riscv_branch:
834835
case RISCV::fixup_riscv_rvc_branch:
835-
case RISCV::fixup_riscv_jal:
836+
case RISCV::fixup_riscv_qc_e_branch:
836837
return false;
837838
}
838839
return true;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp‎

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,8 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
204204
MCRegister Dest = MI.getOperand(1).getReg();
205205
int64_t Imm = MI.getOperand(2).getImm();
206206
addFixup(Fixups, 0, Expr, ELF::R_RISCV_TLSDESC_CALL);
207+
if (STI.hasFeature(RISCV::FeatureRelax))
208+
Fixups.back().setLinkerRelaxable();
207209
MCInst Call =
208210
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
209211

@@ -595,10 +597,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
595597
if (!STI.hasFeature(RISCV::FeatureExactAssembly))
596598
RelaxCandidate = true;
597599
};
598-
auto AsmRelaxToLinkerRelaxableWithFeature = [&](unsigned Feature) -> void {
599-
if (!STI.hasFeature(RISCV::FeatureExactAssembly) && STI.hasFeature(Feature))
600-
RelaxCandidate = true;
601-
};
602600

603601
unsigned FixupKind = RISCV::fixup_riscv_invalid;
604602
if (Kind == MCExpr::Specifier) {
@@ -662,6 +660,9 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
662660
case ELF::R_RISCV_GOT_HI20:
663661
case ELF::R_RISCV_TPREL_HI20:
664662
case ELF::R_RISCV_TLSDESC_HI20:
663+
case ELF::R_RISCV_TLSDESC_LOAD_LO12:
664+
case ELF::R_RISCV_TLSDESC_ADD_LO12:
665+
case ELF::R_RISCV_TLSDESC_CALL:
665666
RelaxCandidate = true;
666667
break;
667668
}
@@ -672,23 +673,24 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
672673
RelaxCandidate = true;
673674
} else if (MIFrm == RISCVII::InstFormatB) {
674675
FixupKind = RISCV::fixup_riscv_branch;
675-
// This might be assembler relaxed to `b<cc>; jal` but we cannot relax
676-
// the `jal` again in the assembler.
676+
// Relaxes to B<cc>; JAL, with fixup_riscv_jal
677+
AsmRelaxToLinkerRelaxable();
677678
} else if (MIFrm == RISCVII::InstFormatCJ) {
678679
FixupKind = RISCV::fixup_riscv_rvc_jump;
680+
// Relaxes to JAL with fixup_riscv_jal
679681
AsmRelaxToLinkerRelaxable();
680682
} else if (MIFrm == RISCVII::InstFormatCB) {
681683
FixupKind = RISCV::fixup_riscv_rvc_branch;
682-
// This might be assembler relaxed to `b<cc>; jal` but we cannot relax
683-
// the `jal` again in the assembler.
684+
// Relaxes to B<cc>; JAL, with fixup_riscv_jal
685+
AsmRelaxToLinkerRelaxable();
684686
} else if (MIFrm == RISCVII::InstFormatCI) {
685687
FixupKind = RISCV::fixup_riscv_rvc_imm;
686688
} else if (MIFrm == RISCVII::InstFormatI) {
687689
FixupKind = RISCV::fixup_riscv_12_i;
688690
} else if (MIFrm == RISCVII::InstFormatQC_EB) {
689691
FixupKind = RISCV::fixup_riscv_qc_e_branch;
690-
// This might be assembler relaxed to `qc.e.b<cc>; jal` but we cannot
691-
// relax the `jal` again in the assembler.
692+
// Relaxes to QC.E.B<cc>I; JAL, with fixup_riscv_jal
693+
AsmRelaxToLinkerRelaxable();
692694
} else if (MIFrm == RISCVII::InstFormatQC_EAI) {
693695
FixupKind = RISCV::fixup_riscv_qc_e_32;
694696
RelaxCandidate = true;
@@ -706,6 +708,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
706708
// If linker relaxation is enabled and supported by this relocation, set a bit
707709
// so that the assembler knows the size of the instruction is not fixed/known,
708710
// and the relocation will need a R_RISCV_RELAX relocation.
711+
LLVM_DEBUG(dbgs() << "Maybe Marking Fixup " << Fixups.back().getKind() << " as Relaxable " << EnableRelax << " " << RelaxCandidate << "\n");
709712
if (EnableRelax && RelaxCandidate)
710713
Fixups.back().setLinkerRelaxable();
711714
++MCNumFixups;

‎llvm/test/CodeGen/RISCV/option-relax-relocation.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
21
; RUN: llc -mtriple=riscv64 -mattr=-relax -filetype=obj < %s \
32
; RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefixes=CHECK,NORELAX
43
; RUN: llc -mtriple=riscv64 -mattr=+relax -filetype=obj < %s \

‎llvm/test/MC/RISCV/Relocations/expr.s‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,12 @@
1010

1111
## This is linker-relaxable to avoid resolving the following fixups
1212
call relax
13+
# CHECK-RELOC: R_RISCV_CALL_PLT
14+
# CHECK-RELOC-NEXT: R_RISCV_RELAX
1315

1416
jal zero, .LBB0+16
1517
# CHECK-INSTR: jal zero, 0x10
16-
# CHECK-RELOC: R_RISCV_JAL
18+
# CHECK-RELOC-NEXT: R_RISCV_JAL
1719
# CHECK-RELOC-NEXT: R_RISCV_RELAX
1820

1921
beq a0, a1, .LBB1+32
@@ -25,12 +27,12 @@ c.j .+32
2527

2628
c.j .LBB2+4
2729
# CHECK-INSTR: c.j 0x22
28-
# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP
30+
# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP
2931

3032
c.beqz a0, .-2
3133
# CHECK-INSTR: c.beqz a0, 0x12
3234

3335
call relax
34-
# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT
35-
# CHECK-RELOC-NEXT: R_RISCV_RELAX
36+
# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT
37+
# CHECK-RELOC-NEXT: R_RISCV_RELAX
3638
.LBB2:

‎llvm/test/MC/RISCV/Relocations/relocations.s‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,19 +2,25 @@
22
# RUN: | FileCheck -check-prefix=INSTR %s
33
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c %s \
44
# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s
5+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax %s \
6+
# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC-RELAX %s
57

68
# Check prefixes:
79
# RELOC - Check the relocation in the object.
10+
# RELOC-RELAX - Check the relocation in the object with relaxations
811
# INSTR - Check the instruction is handled properly by the ASMPrinter
912

1013
.long foo
1114
# RELOC: R_RISCV_32 foo
15+
# RELOC-RELAX: R_RISCV_32 foo
1216

1317
.quad foo
1418
# RELOC: R_RISCV_64 foo
19+
# RELOC-RELAX: R_RISCV_64 foo
1520

1621
lui t1, %hi(foo)
1722
# RELOC: R_RISCV_HI20 foo 0x0
23+
# RELOC
1824
# INSTR: lui t1, %hi(foo)
1925

2026
lui t1, %hi(foo+4)

‎llvm/test/MC/RISCV/align.s‎

Lines changed: 17 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -137,8 +137,14 @@ data2:
137137
add a0, a0, a1
138138

139139
## Branches crossing the linker-relaxable R_RISCV_ALIGN need relocations.
140-
# RELAX-RELOC-NOT: .rela.text3 {
141-
# C-OR-ZCA-EXT-RELAX-RELOC-NOT: .rela.text3 {
140+
# RELAX-RELOC: .rela.text3 {
141+
# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0
142+
# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0
143+
# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6
144+
# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0
145+
# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0
146+
# RELAX-RELOC-NEXT: }
147+
# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3 {
142148
.section .text3, "ax"
143149
bnez t1, 1f
144150
bnez t2, 2f
@@ -153,9 +159,11 @@ data2:
153159
# RELAX-RELOC: .rela.text3a {
154160
# RELAX-RELOC-NEXT: 0x0 R_RISCV_CALL_PLT foo 0x0
155161
# RELAX-RELOC-NEXT: 0x0 R_RISCV_RELAX - 0x0
162+
# RELAX-RELOC-NEXT: 0x8 R_RISCV_BRANCH .Ltmp[[#]] 0x0
156163
# RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0
157164
# RELAX-RELOC-NEXT: 0x10 R_RISCV_ALIGN - 0x6
158165
# RELAX-RELOC-NEXT: 0x16 R_RISCV_BRANCH .Ltmp[[#]] 0x0
166+
# RELAX-RELOC-NEXT: 0x1A R_RISCV_BRANCH .Ltmp[[#]] 0x0
159167
# RELAX-RELOC-NEXT: }
160168
# C-OR-ZCA-EXT-NORELAX-RELOC: .rela.text3a
161169
# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3a
@@ -171,8 +179,13 @@ bnez t1, 2b
171179

172180
## .text3 with a call at the end
173181
# RELAX-RELOC: .rela.text3b {
174-
# RELAX-RELOC-NEXT: 0x10 R_RISCV_CALL_PLT foo 0x0
175-
# RELAX-RELOC-NEXT: 0x10 R_RISCV_RELAX - 0x0
182+
# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0
183+
# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0
184+
# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6
185+
# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0
186+
# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0
187+
# RELAX-RELOC-NEXT: 0x16 R_RISCV_CALL_PLT foo 0x0
188+
# RELAX-RELOC-NEXT: 0x16 R_RISCV_RELAX - 0x0
176189
# RELAX-RELOC-NEXT: }
177190
.section .text3b, "ax"
178191
bnez t1, 1f

‎llvm/test/MC/RISCV/long-conditional-jump.s‎

Lines changed: 40 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
# RUN: llvm-mc -filetype=obj -triple=riscv64 %s \
2-
# RUN: | llvm-objdump -d -M no-aliases - \
2+
# RUN: | llvm-objdump -dr -M no-aliases - \
33
# RUN: | FileCheck --check-prefix=CHECK-INST %s
44
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c %s \
5-
# RUN: | llvm-objdump -d -M no-aliases - \
5+
# RUN: | llvm-objdump -dr -M no-aliases - \
66
# RUN: | FileCheck --check-prefix=CHECK-INST-C %s
77
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s \
88
# RUN: | llvm-objdump -dr -M no-aliases - \
@@ -21,9 +21,11 @@ test:
2121
# CHECK-INST-RELAX: beq a0, a1, 0x8
2222
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
2323
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L1
24+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
2425
# CHECK-INST-C-RELAX: beq a0, a1, 0x8
2526
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
2627
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L1
28+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
2729
bne a0, a1, .L1
2830
call relax
2931
.fill 1300-2, 4, 0
@@ -35,8 +37,12 @@ test:
3537
# CHECK-INST-C-NEXT: jal zero, 0x28b2
3638
# CHECK-INST-RELAX: bne a0, a1, 0x1464
3739
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
40+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L2
41+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
3842
# CHECK-INST-C-RELAX: bne a0, a1, 0x1462
3943
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
44+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L2
45+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
4046
beq a0, a1, .L2
4147
.fill 1300, 4, 0
4248
.L2:
@@ -47,8 +53,12 @@ test:
4753
# CHECK-INST-C-NEXT: jal zero, 0x3d0c
4854
# CHECK-INST-RELAX: bge a0, a1, 0x28c0
4955
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
56+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L3
57+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
5058
# CHECK-INST-C-RELAX: bge a0, a1, 0x28bc
5159
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
60+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L3
61+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
5262
blt a0, a1, .L3
5363
.fill 1300, 4, 0
5464
.L3:
@@ -59,8 +69,12 @@ test:
5969
# CHECK-INST-C-NEXT: jal zero, 0x5166
6070
# CHECK-INST-RELAX: blt a0, a1, 0x3d1c
6171
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
72+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L4
73+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
6274
# CHECK-INST-C-RELAX: blt a0, a1, 0x3d16
6375
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
76+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L4
77+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
6478
bge a0, a1, .L4
6579
.fill 1300, 4, 0
6680
.L4:
@@ -71,8 +85,12 @@ test:
7185
# CHECK-INST-C-NEXT: jal zero, 0x65c0
7286
# CHECK-INST-RELAX: bgeu a0, a1, 0x5178
7387
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
88+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L5
89+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
7490
# CHECK-INST-C-RELAX: bgeu a0, a1, 0x5170
7591
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
92+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L5
93+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
7694
bltu a0, a1, .L5
7795
.fill 1300, 4, 0
7896
.L5:
@@ -83,8 +101,12 @@ test:
83101
# CHECK-INST-C-NEXT: jal zero, 0x7a1a
84102
# CHECK-INST-RELAX: bltu a0, a1, 0x65d4
85103
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
104+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L6
105+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
86106
# CHECK-INST-C-RELAX: bltu a0, a1, 0x65ca
87107
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
108+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L6
109+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
88110
bgeu a0, a1, .L6
89111
.fill 1300, 4, 0
90112
.L6:
@@ -95,8 +117,12 @@ test:
95117
# CHECK-INST-C-NEXT: jal zero, 0x8e72
96118
# CHECK-INST-RELAX: bne a0, zero, 0x7a30
97119
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
120+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L7
121+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
98122
# CHECK-INST-C-RELAX: c.bnez a0, 0x7a22
99123
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
124+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L7
125+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
100126
beqz a0, .L7
101127
.fill 1300, 4, 0
102128
.L7:
@@ -107,8 +133,12 @@ test:
107133
# CHECK-INST-C-NEXT: jal zero, 0xa2ca
108134
# CHECK-INST-RELAX: bne zero, a0, 0x8e8c
109135
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
136+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L8
137+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
110138
# CHECK-INST-C-RELAX: c.bnez a0, 0x8e7a
111139
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
140+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L8
141+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
112142
beq x0, a0, .L8
113143
.fill 1300, 4, 0
114144
.L8:
@@ -119,8 +149,12 @@ test:
119149
# CHECK-INST-C-NEXT: jal zero, 0xb722
120150
# CHECK-INST-RELAX: beq a0, zero, 0xa2e8
121151
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
152+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L9
153+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
122154
# CHECK-INST-C-RELAX: c.beqz a0, 0xa2d2
123155
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
156+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L9
157+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
124158
bnez a0, .L9
125159
.fill 1300, 4, 0
126160
.L9:
@@ -131,8 +165,12 @@ test:
131165
# CHECK-INST-C-NEXT: jal zero, 0xcb7c
132166
# CHECK-INST-RELAX: beq a6, zero, 0xb744
133167
# CHECK-INST-RELAX-NEXT: jal zero, {{.*}}
168+
# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L10
169+
# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS*
134170
# CHECK-INST-C-RELAX: beq a6, zero, 0xb72c
135171
# CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}}
172+
# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L10
173+
# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS*
136174
bnez x16, .L10
137175
.fill 1300, 4, 0
138176
.L10:

‎llvm/test/MC/RISCV/tlsdesc.s‎

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,32 @@
1-
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s --defsym RV32=1 | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV32
2-
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV64
1+
# RUN: llvm-mc -filetype=obj -triple riscv32 < %s --defsym RV32=1 \
2+
# RUN: | llvm-objdump -dr -M no-aliases - \
3+
# RUN: | FileCheck %s --check-prefixes=INST,RV32
4+
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
5+
# RUN: | llvm-objdump -dr -M no-aliases - \
6+
# RUN: | FileCheck %s --check-prefixes=INST,RV64
7+
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s --defsym RV32=1 \
8+
# RUN: | llvm-objdump -dr -M no-aliases - \
9+
# RUN: | FileCheck %s --check-prefixes=INST,RV32,RELAX
10+
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+relax < %s \
11+
# RUN: | llvm-objdump -dr -M no-aliases - \
12+
# RUN: | FileCheck %s --check-prefixes=INST,RV64,RELAX
313

4-
# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR
5-
# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR
14+
# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 \
15+
# RUN: | FileCheck %s --check-prefixes=ERR
16+
# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 \
17+
# RUN: | FileCheck %s --check-prefixes=ERR
618

719
start: # @start
820
# %bb.0: # %entry
921
.Ltlsdesc_hi0:
1022
auipc a0, %tlsdesc_hi(a-4)
1123
# INST: auipc a0, 0x0
1224
# INST-NEXT: R_RISCV_TLSDESC_HI20 a-0x4
25+
# RELAX-NEXT: R_RISCV_RELAX
1326
auipc a0, %tlsdesc_hi(unspecified)
1427
# INST-NEXT: auipc a0, 0x0
1528
# INST-NEXT: R_RISCV_TLSDESC_HI20 unspecified
29+
# RELAX-NEXT: R_RISCV_RELAX
1630
.ifdef RV32
1731
lw a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0)
1832
# RV32: lw a1, 0x0(a0)
@@ -22,12 +36,15 @@ start: # @start
2236
# RV64: ld a1, 0x0(a0)
2337
# RV64-NEXT: R_RISCV_TLSDESC_LOAD_LO12 .Ltlsdesc_hi0
2438
.endif
39+
# RELAX-NEXT: R_RISCV_RELAX
2540
addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0)
2641
# INST: addi a0, a0, 0x0
2742
# INST-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi0
43+
# RELAX-NEXT: R_RISCV_RELAX
2844
jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0)
2945
# INST-NEXT: jalr t0, 0x0(a1)
3046
# INST-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi0
47+
# RELAX-NEXT: R_RISCV_RELAX
3148
add a0, a0, tp
3249
# INST-NEXT: add a0, a0, tp
3350
ret

‎llvm/test/MC/RISCV/xqcibi-linker-relaxation.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -61,9 +61,9 @@ mid_jump_over_fixed:
6161
.space 0x1000
6262
# CHECK-NEXT: ...
6363
j mid_jump_over_fixed
64-
# CHECK-NEXT: jal zero, 0x24 <mid_jump_over_fixed>
65-
# CHECK-NOT: R_RISCV_JAL
66-
# CHECK-NOT: R_RISCV_RELAX
64+
# CHECK-NEXT: jal zero, 0x1026 <mid_jump_over_fixed+0x1002>
65+
# CHECK-NEXT: R_RISCV_JAL mid_jump_over_fixed
66+
# CHECK-NEXT: R_RISCV_RELAX *ABS*
6767
ret
6868
# CHECK-NEXT: c.jr ra
6969

@@ -79,6 +79,6 @@ mid_jump_over_relaxable:
7979
j mid_jump_over_relaxable
8080
# CHECK-NEXT: jal zero, 0x2034 <mid_jump_over_relaxable+0x1008>
8181
# CHECK-NEXT: R_RISCV_JAL mid_jump_over_relaxable
82-
# CHECK-NOT: R_RISCV_RELAX
82+
# CHECK-NEXT: R_RISCV_RELAX
8383
ret
8484
# CHECK-NEXT: c.jr ra

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