Skip to content

Commit 784f258

Browse files
aqjuneaqjune
committed
Precommit test files for D105344 (NFC)
1 parent 3223d41 commit 784f258

File tree

1 file changed

+210
-0
lines changed

1 file changed

+210
-0
lines changed

‎llvm/test/CodeGen/X86/setcc-freeze.ll

Lines changed: 210 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,210 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
3+
4+
define i32 @f(i16* %p) {
5+
; CHECK-LABEL: f:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: movzwl (%rdi), %eax
8+
; CHECK-NEXT: andl $2048, %eax # imm = 0x800
9+
; CHECK-NEXT: testw %ax, %ax
10+
; CHECK-NEXT: je .LBB0_1
11+
; CHECK-NEXT: # %bb.2: # %B
12+
; CHECK-NEXT: movl $20, %eax
13+
; CHECK-NEXT: retq
14+
; CHECK-NEXT: .LBB0_1: # %A
15+
; CHECK-NEXT: movl $10, %eax
16+
; CHECK-NEXT: retq
17+
%v = load i16, i16* %p, align 2
18+
%and = and i16 %v, 2048
19+
%cond = icmp eq i16 %and, 0
20+
%cond.fr = freeze i1 %cond
21+
br i1 %cond.fr, label %A, label %B
22+
A:
23+
ret i32 10
24+
B:
25+
ret i32 20
26+
}
27+
28+
define i32 @f_false(i16* %p) {
29+
; CHECK-LABEL: f_false:
30+
; CHECK: # %bb.0:
31+
; CHECK-NEXT: movb $1, %al
32+
; CHECK-NEXT: testb %al, %al
33+
; CHECK-NEXT: jne .LBB1_2
34+
; CHECK-NEXT: # %bb.1: # %A
35+
; CHECK-NEXT: movl $10, %eax
36+
; CHECK-NEXT: retq
37+
; CHECK-NEXT: .LBB1_2: # %B
38+
; CHECK-NEXT: movl $20, %eax
39+
; CHECK-NEXT: retq
40+
%v = load i16, i16* %p, align 2
41+
%and = and i16 %v, 2048
42+
%cond = icmp ult i16 %and, 0
43+
%cond.fr = freeze i1 %cond
44+
br i1 %cond.fr, label %A, label %B
45+
A:
46+
ret i32 10
47+
B:
48+
ret i32 20
49+
}
50+
51+
define i32 @f_false2(i16* %p) {
52+
; CHECK-LABEL: f_false2:
53+
; CHECK: # %bb.0:
54+
; CHECK-NEXT: movb $1, %al
55+
; CHECK-NEXT: testb %al, %al
56+
; CHECK-NEXT: jne .LBB2_2
57+
; CHECK-NEXT: # %bb.1: # %A
58+
; CHECK-NEXT: movl $10, %eax
59+
; CHECK-NEXT: retq
60+
; CHECK-NEXT: .LBB2_2: # %B
61+
; CHECK-NEXT: movl $20, %eax
62+
; CHECK-NEXT: retq
63+
%v = load i16, i16* %p, align 2
64+
%and = and i16 %v, 2048
65+
%cond = icmp ult i16 65535, %and
66+
%cond.fr = freeze i1 %cond
67+
br i1 %cond.fr, label %A, label %B
68+
A:
69+
ret i32 10
70+
B:
71+
ret i32 20
72+
}
73+
74+
define i32 @f_false3(i16* %p) {
75+
; CHECK-LABEL: f_false3:
76+
; CHECK: # %bb.0:
77+
; CHECK-NEXT: movb $1, %al
78+
; CHECK-NEXT: testb %al, %al
79+
; CHECK-NEXT: jne .LBB3_2
80+
; CHECK-NEXT: # %bb.1: # %A
81+
; CHECK-NEXT: movl $10, %eax
82+
; CHECK-NEXT: retq
83+
; CHECK-NEXT: .LBB3_2: # %B
84+
; CHECK-NEXT: movl $20, %eax
85+
; CHECK-NEXT: retq
86+
%v = load i16, i16* %p, align 2
87+
%and = and i16 %v, 2048
88+
%cond = icmp slt i16 32767, %and
89+
%cond.fr = freeze i1 %cond
90+
br i1 %cond.fr, label %A, label %B
91+
A:
92+
ret i32 10
93+
B:
94+
ret i32 20
95+
}
96+
97+
define i32 @f_false4(i16* %p) {
98+
; CHECK-LABEL: f_false4:
99+
; CHECK: # %bb.0:
100+
; CHECK-NEXT: movb $1, %al
101+
; CHECK-NEXT: testb %al, %al
102+
; CHECK-NEXT: jne .LBB4_2
103+
; CHECK-NEXT: # %bb.1: # %A
104+
; CHECK-NEXT: movl $10, %eax
105+
; CHECK-NEXT: retq
106+
; CHECK-NEXT: .LBB4_2: # %B
107+
; CHECK-NEXT: movl $20, %eax
108+
; CHECK-NEXT: retq
109+
%v = load i16, i16* %p, align 2
110+
%and = and i16 %v, 2048
111+
%cond = icmp sgt i16 %and, 32767
112+
%cond.fr = freeze i1 %cond
113+
br i1 %cond.fr, label %A, label %B
114+
A:
115+
ret i32 10
116+
B:
117+
ret i32 20
118+
}
119+
120+
define i32 @f_true(i16* %p) {
121+
; CHECK-LABEL: f_true:
122+
; CHECK: # %bb.0:
123+
; CHECK-NEXT: xorl %eax, %eax
124+
; CHECK-NEXT: testb %al, %al
125+
; CHECK-NEXT: jne .LBB5_2
126+
; CHECK-NEXT: # %bb.1: # %A
127+
; CHECK-NEXT: movl $10, %eax
128+
; CHECK-NEXT: retq
129+
; CHECK-NEXT: .LBB5_2: # %B
130+
; CHECK-NEXT: movl $20, %eax
131+
; CHECK-NEXT: retq
132+
%v = load i16, i16* %p, align 2
133+
%and = and i16 %v, 2048
134+
%cond = icmp sge i16 %and, -32768
135+
%cond.fr = freeze i1 %cond
136+
br i1 %cond.fr, label %A, label %B
137+
A:
138+
ret i32 10
139+
B:
140+
ret i32 20
141+
}
142+
143+
define i32 @f_true2(i16* %p) {
144+
; CHECK-LABEL: f_true2:
145+
; CHECK: # %bb.0:
146+
; CHECK-NEXT: xorl %eax, %eax
147+
; CHECK-NEXT: testb %al, %al
148+
; CHECK-NEXT: jne .LBB6_2
149+
; CHECK-NEXT: # %bb.1: # %A
150+
; CHECK-NEXT: movl $10, %eax
151+
; CHECK-NEXT: retq
152+
; CHECK-NEXT: .LBB6_2: # %B
153+
; CHECK-NEXT: movl $20, %eax
154+
; CHECK-NEXT: retq
155+
%v = load i16, i16* %p, align 2
156+
%and = and i16 %v, 2048
157+
%cond = icmp uge i16 %and, 0
158+
%cond.fr = freeze i1 %cond
159+
br i1 %cond.fr, label %A, label %B
160+
A:
161+
ret i32 10
162+
B:
163+
ret i32 20
164+
}
165+
166+
define i32 @f_true3(i16* %p) {
167+
; CHECK-LABEL: f_true3:
168+
; CHECK: # %bb.0:
169+
; CHECK-NEXT: xorl %eax, %eax
170+
; CHECK-NEXT: testb %al, %al
171+
; CHECK-NEXT: jne .LBB7_2
172+
; CHECK-NEXT: # %bb.1: # %A
173+
; CHECK-NEXT: movl $10, %eax
174+
; CHECK-NEXT: retq
175+
; CHECK-NEXT: .LBB7_2: # %B
176+
; CHECK-NEXT: movl $20, %eax
177+
; CHECK-NEXT: retq
178+
%v = load i16, i16* %p, align 2
179+
%and = and i16 %v, 2048
180+
%cond = icmp ule i16 0, %and
181+
%cond.fr = freeze i1 %cond
182+
br i1 %cond.fr, label %A, label %B
183+
A:
184+
ret i32 10
185+
B:
186+
ret i32 20
187+
}
188+
189+
define i32 @f_true4(i16* %p) {
190+
; CHECK-LABEL: f_true4:
191+
; CHECK: # %bb.0:
192+
; CHECK-NEXT: xorl %eax, %eax
193+
; CHECK-NEXT: testb %al, %al
194+
; CHECK-NEXT: jne .LBB8_2
195+
; CHECK-NEXT: # %bb.1: # %A
196+
; CHECK-NEXT: movl $10, %eax
197+
; CHECK-NEXT: retq
198+
; CHECK-NEXT: .LBB8_2: # %B
199+
; CHECK-NEXT: movl $20, %eax
200+
; CHECK-NEXT: retq
201+
%v = load i16, i16* %p, align 2
202+
%and = and i16 %v, 2048
203+
%cond = icmp ule i16 %and, 65535
204+
%cond.fr = freeze i1 %cond
205+
br i1 %cond.fr, label %A, label %B
206+
A:
207+
ret i32 10
208+
B:
209+
ret i32 20
210+
}

0 commit comments

Comments
 (0)