Rename ScalarizeV2S16 to WidenV2S16ToS32

gandhi56 · gandhi56 · commit 789eaad0c5e9 · 2025-10-21T09:18:25.000-05:00
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -500,7 +500,7 @@ void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
   MI.eraseFromParent();
 }
 
-void RegBankLegalizeHelper::lowerScalarizeV2S16(MachineInstr &MI) {
+void RegBankLegalizeHelper::lowerV2S16ViaS32Widening(MachineInstr &MI) {
   auto Op1 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(1).getReg());
   auto Hi1 = Op1.getReg(0);
   auto Lo1 = Op1.getReg(1);
@@ -826,7 +826,7 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
     break;
   }
   case ScalarizeV2S16:
-    return lowerScalarizeV2S16(MI);
+    return lowerV2S16ViaS32Widening(MI);
   case WidenMMOToS32:
     return widenMMOToS32(cast<GAnyLoad>(MI));
   }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
@@ -125,7 +125,7 @@ class RegBankLegalizeHelper {
   void lowerSplitTo32Select(MachineInstr &MI);
   void lowerSplitTo32SExtInReg(MachineInstr &MI);
   void lowerUnpackMinMax(MachineInstr &MI);
-  void lowerScalarizeV2S16(MachineInstr &MI);
+  void lowerV2S16ViaS32Widening(MachineInstr &MI);
 };
 
 } // end namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -471,7 +471,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
       .Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
       .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
-      .Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, ScalarizeV2S16})
+      .Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, WidenV2S16ToS32})
       .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
       .Uni(S64, {{Sgpr64}, {Sgpr64, Sgpr64}})
       .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}});
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -224,7 +224,7 @@ enum LoweringMethodID {
   SplitLoad,
   WidenLoad,
   WidenMMOToS32,
-  ScalarizeV2S16
+  WidenV2S16ToS32
 };
 
 enum FastRulesTypes {

Original file line number	Diff line number	Diff line change
`@@ -500,7 +500,7 @@ void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {`
`500`	`500`	`MI.eraseFromParent();`
`501`	`501`	`}`
`502`	`502`
`503`		`-void RegBankLegalizeHelper::lowerScalarizeV2S16(MachineInstr &MI) {`
	`503`	`+void RegBankLegalizeHelper::lowerV2S16ViaS32Widening(MachineInstr &MI) {`
`504`	`504`	`auto Op1 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(1).getReg());`
`505`	`505`	`auto Hi1 = Op1.getReg(0);`
`506`	`506`	`auto Lo1 = Op1.getReg(1);`
`@@ -826,7 +826,7 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,`
`826`	`826`	`break;`
`827`	`827`	`}`
`828`	`828`	`case ScalarizeV2S16:`
`829`		`- return lowerScalarizeV2S16(MI);`
	`829`	`+ return lowerV2S16ViaS32Widening(MI);`
`830`	`830`	`case WidenMMOToS32:`
`831`	`831`	`return widenMMOToS32(cast<GAnyLoad>(MI));`
`832`	`832`	`}`