fix test

broxigarchen · broxigarchen · commit 78a1088efc36 · 2025-03-15T00:34:28.000-04:00
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -188,7 +188,8 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
     OutMI.addOperand(Src);
     return;
   } else if (const auto *Info = AMDGPU::getT16D16Helper(Opcode)) {
-    uint16_t OpName = AMDGPU::OpName::OPERAND_LAST;
+    const SIRegisterInfo &TRI = TII->getRegisterInfo();
+    llvm::AMDGPU::OpName OpName;
     if (TII->isDS(Opcode)) {
       if (MI->mayLoad())
         OpName = llvm::AMDGPU::OpName::vdst;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
@@ -239,53 +239,48 @@ define amdgpu_kernel void @store_lds_v4i32_align1(ptr addrspace(3) %out, <4 x i3
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_and_b32 s6, 0xffff, s0
 ; GFX11-NEXT:    s_lshr_b32 s5, s0, 16
-; GFX11-NEXT:    v_mov_b16_e32 v0.l, s0
-; GFX11-NEXT:    v_mov_b32_e32 v5, s4
+; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s4
 ; GFX11-NEXT:    s_lshr_b32 s0, s1, 16
 ; GFX11-NEXT:    s_and_b32 s4, 0xffff, s1
-; GFX11-NEXT:    v_mov_b16_e32 v0.h, s1
+; GFX11-NEXT:    v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s2
 ; GFX11-NEXT:    s_lshr_b32 s1, s2, 16
 ; GFX11-NEXT:    s_and_b32 s7, 0xffff, s2
-; GFX11-NEXT:    v_mov_b16_e32 v1.l, s2
 ; GFX11-NEXT:    s_lshr_b32 s2, s6, 8
 ; GFX11-NEXT:    s_lshr_b32 s6, s5, 8
-; GFX11-NEXT:    v_mov_b16_e32 v2.h, s2
-; GFX11-NEXT:    v_mov_b16_e32 v1.h, s5
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s6
+; GFX11-NEXT:    v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s0
 ; GFX11-NEXT:    s_lshr_b32 s4, s4, 8
 ; GFX11-NEXT:    s_lshr_b32 s5, s0, 8
-; GFX11-NEXT:    v_mov_b16_e32 v2.l, s0
 ; GFX11-NEXT:    s_lshr_b32 s0, s7, 8
-; GFX11-NEXT:    v_mov_b16_e32 v3.l, s6
-; GFX11-NEXT:    v_mov_b16_e32 v3.h, s4
-; GFX11-NEXT:    v_mov_b16_e32 v4.l, s5
-; GFX11-NEXT:    ds_store_b8 v5, v0
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v2 offset:1
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v1 offset:2
-; GFX11-NEXT:    ds_store_b8 v5, v3 offset:3
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v0 offset:4
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v3 offset:5
-; GFX11-NEXT:    ds_store_b8 v5, v2 offset:6
-; GFX11-NEXT:    ds_store_b8 v5, v4 offset:7
-; GFX11-NEXT:    v_mov_b16_e32 v0.l, s0
+; GFX11-NEXT:    v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v9, s5
+; GFX11-NEXT:    ds_store_b8 v1, v0
+; GFX11-NEXT:    ds_store_b8 v1, v6 offset:1
+; GFX11-NEXT:    ds_store_b8 v1, v4 offset:2
+; GFX11-NEXT:    ds_store_b8 v1, v7 offset:3
+; GFX11-NEXT:    ds_store_b8 v1, v2 offset:4
+; GFX11-NEXT:    ds_store_b8 v1, v8 offset:5
+; GFX11-NEXT:    ds_store_b8 v1, v5 offset:6
+; GFX11-NEXT:    ds_store_b8 v1, v9 offset:7
+; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v5, s3
 ; GFX11-NEXT:    s_lshr_b32 s0, s1, 8
-; GFX11-NEXT:    v_mov_b16_e32 v0.h, s1
-; GFX11-NEXT:    v_mov_b16_e32 v1.h, s0
+; GFX11-NEXT:    v_mov_b32_e32 v2, s1
+; GFX11-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX11-NEXT:    s_and_b32 s0, 0xffff, s3
 ; GFX11-NEXT:    s_lshr_b32 s1, s3, 16
 ; GFX11-NEXT:    s_lshr_b32 s0, s0, 8
-; GFX11-NEXT:    v_mov_b16_e32 v2.l, s3
-; GFX11-NEXT:    v_mov_b16_e32 v2.h, s0
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
 ; GFX11-NEXT:    s_lshr_b32 s0, s1, 8
-; GFX11-NEXT:    v_mov_b16_e32 v3.l, s1
-; GFX11-NEXT:    v_mov_b16_e32 v3.h, s0
-; GFX11-NEXT:    ds_store_b8 v5, v1 offset:8
-; GFX11-NEXT:    ds_store_b8 v5, v0 offset:9
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v0 offset:10
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v1 offset:11
-; GFX11-NEXT:    ds_store_b8 v5, v2 offset:12
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v2 offset:13
-; GFX11-NEXT:    ds_store_b8 v5, v3 offset:14
-; GFX11-NEXT:    ds_store_b8_d16_hi v5, v3 offset:15
+; GFX11-NEXT:    v_mov_b32_e32 v8, s0
+; GFX11-NEXT:    ds_store_b8 v1, v3 offset:8
+; GFX11-NEXT:    ds_store_b8 v1, v0 offset:9
+; GFX11-NEXT:    ds_store_b8 v1, v2 offset:10
+; GFX11-NEXT:    ds_store_b8 v1, v4 offset:11
+; GFX11-NEXT:    ds_store_b8 v1, v5 offset:12
+; GFX11-NEXT:    ds_store_b8 v1, v6 offset:13
+; GFX11-NEXT:    ds_store_b8 v1, v7 offset:14
+; GFX11-NEXT:    ds_store_b8 v1, v8 offset:15
 ; GFX11-NEXT:    s_endpgm
   store <4 x i32> %x, ptr addrspace(3) %out, align 1
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
@@ -207,42 +207,36 @@ define amdgpu_kernel void @store_lds_v3i32_align1(ptr addrspace(3) %out, <3 x i3
 ; GFX11-NEXT:    s_load_b32 s3, s[4:5], 0x0
 ; GFX11-NEXT:    s_and_b32 s5, 0xffff, s0
 ; GFX11-NEXT:    s_lshr_b32 s4, s0, 16
-; GFX11-NEXT:    v_mov_b16_e32 v0.l, s0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_mov_b32_e32 v6, s3
+; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s3
 ; GFX11-NEXT:    s_lshr_b32 s0, s1, 16
 ; GFX11-NEXT:    s_and_b32 s3, 0xffff, s1
-; GFX11-NEXT:    v_mov_b16_e32 v0.h, s1
+; GFX11-NEXT:    v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s2
 ; GFX11-NEXT:    s_lshr_b32 s1, s2, 16
 ; GFX11-NEXT:    s_and_b32 s6, 0xffff, s2
-; GFX11-NEXT:    v_mov_b16_e32 v1.l, s2
 ; GFX11-NEXT:    s_lshr_b32 s2, s5, 8
 ; GFX11-NEXT:    s_lshr_b32 s5, s4, 8
-; GFX11-NEXT:    v_mov_b16_e32 v3.l, s2
-; GFX11-NEXT:    v_mov_b16_e32 v1.h, s4
+; GFX11-NEXT:    v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v7, s2
+; GFX11-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s0
 ; GFX11-NEXT:    s_lshr_b32 s3, s3, 8
 ; GFX11-NEXT:    s_lshr_b32 s4, s0, 8
-; GFX11-NEXT:    v_mov_b16_e32 v2.l, s0
 ; GFX11-NEXT:    s_lshr_b32 s0, s6, 8
 ; GFX11-NEXT:    s_lshr_b32 s6, s1, 8
-; GFX11-NEXT:    v_mov_b16_e32 v3.h, s5
-; GFX11-NEXT:    v_mov_b16_e32 v2.h, s1
-; GFX11-NEXT:    v_mov_b16_e32 v4.l, s3
-; GFX11-NEXT:    v_mov_b16_e32 v4.h, s4
-; GFX11-NEXT:    v_mov_b16_e32 v5.l, s0
-; GFX11-NEXT:    v_mov_b16_e32 v5.h, s6
-; GFX11-NEXT:    ds_store_b8 v6, v0
-; GFX11-NEXT:    ds_store_b8 v6, v3 offset:1
-; GFX11-NEXT:    ds_store_b8_d16_hi v6, v1 offset:2
-; GFX11-NEXT:    ds_store_b8_d16_hi v6, v3 offset:3
-; GFX11-NEXT:    ds_store_b8_d16_hi v6, v0 offset:4
-; GFX11-NEXT:    ds_store_b8 v6, v4 offset:5
-; GFX11-NEXT:    ds_store_b8 v6, v2 offset:6
-; GFX11-NEXT:    ds_store_b8_d16_hi v6, v4 offset:7
-; GFX11-NEXT:    ds_store_b8 v6, v1 offset:8
-; GFX11-NEXT:    ds_store_b8 v6, v5 offset:9
-; GFX11-NEXT:    ds_store_b8_d16_hi v6, v2 offset:10
-; GFX11-NEXT:    ds_store_b8_d16_hi v6, v5 offset:11
+; GFX11-NEXT:    v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v9, s3
+; GFX11-NEXT:    v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s0
+; GFX11-NEXT:    v_mov_b32_e32 v12, s6
+; GFX11-NEXT:    ds_store_b8 v1, v0
+; GFX11-NEXT:    ds_store_b8 v1, v7 offset:1
+; GFX11-NEXT:    ds_store_b8 v1, v4 offset:2
+; GFX11-NEXT:    ds_store_b8 v1, v8 offset:3
+; GFX11-NEXT:    ds_store_b8 v1, v2 offset:4
+; GFX11-NEXT:    ds_store_b8 v1, v9 offset:5
+; GFX11-NEXT:    ds_store_b8 v1, v5 offset:6
+; GFX11-NEXT:    ds_store_b8 v1, v10 offset:7
+; GFX11-NEXT:    ds_store_b8 v1, v3 offset:8
+; GFX11-NEXT:    ds_store_b8 v1, v11 offset:9
+; GFX11-NEXT:    ds_store_b8 v1, v6 offset:10
+; GFX11-NEXT:    ds_store_b8 v1, v12 offset:11
 ; GFX11-NEXT:    s_endpgm
   store <3 x i32> %x, ptr addrspace(3) %out, align 1
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
@@ -229,11 +229,10 @@ define amdgpu_kernel void @add_x_shl_max_offset() #1 {
 ;
 ; GFX11-LABEL: add_x_shl_max_offset:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-NEXT:    v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 4, v0
-; GFX11-NEXT:    v_mov_b16_e32 v0.l, 13
-; GFX11-NEXT:    ds_store_b8 v1, v0 offset:65535
+; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
+; GFX11-NEXT:    ds_store_b8 v0, v1 offset:65535
 ; GFX11-NEXT:    s_endpgm
   %x.i = tail call i32 @llvm.amdgcn.workitem.id.x()
   %shl = shl i32 %x.i, 4
@@ -274,12 +273,11 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_alt() #1 {
 ;
 ; GFX11-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-NEXT:    v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-NEXT:    v_xor_b32_e32 v1, 0xffff, v0
-; GFX11-NEXT:    v_mov_b16_e32 v0.l, 13
-; GFX11-NEXT:    ds_store_b8 v1, v0
+; GFX11-NEXT:    v_xor_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT:    ds_store_b8 v0, v1
 ; GFX11-NEXT:    s_endpgm
   %x.i = tail call i32 @llvm.amdgcn.workitem.id.x()
   %.neg = mul i32 %x.i, -4
@@ -320,12 +318,11 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_not_canonical() #1 {
 ;
 ; GFX11-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-NEXT:    v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-NEXT:    v_xor_b32_e32 v1, 0xffff, v0
-; GFX11-NEXT:    v_mov_b16_e32 v0.l, 13
-; GFX11-NEXT:    ds_store_b8 v1, v0
+; GFX11-NEXT:    v_xor_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT:    ds_store_b8 v0, v1
 ; GFX11-NEXT:    s_endpgm
   %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
   %neg = sub i32 0, %x.i
@@ -364,12 +361,11 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_p1() #1 {
 ;
 ; GFX11-LABEL: add_x_shl_neg_to_sub_max_offset_p1:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-NEXT:    v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX11-NEXT:    v_sub_nc_u32_e32 v1, 0x10000, v0
-; GFX11-NEXT:    v_mov_b16_e32 v0.l, 13
-; GFX11-NEXT:    ds_store_b8 v1, v0
+; GFX11-NEXT:    v_sub_nc_u32_e32 v0, 0x10000, v0
+; GFX11-NEXT:    ds_store_b8 v0, v1
 ; GFX11-NEXT:    s_endpgm
   %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
   %neg = sub i32 0, %x.i
