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[LoongArch] Lowering v32i8 vector mask generation to VMSKLTZ (#149953)
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2 files changed

+71
-1188
lines changed

2 files changed

+71
-1188
lines changed

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 20 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4794,13 +4794,29 @@ static SDValue performBITCASTCombine(SDNode *N, SelectionDAG &DAG,
47944794
UseLASX = true;
47954795
break;
47964796
};
4797-
if (UseLASX && !(Subtarget.has32S() && Subtarget.hasExtLASX()))
4798-
return SDValue();
47994797
Src = PropagateSExt ? signExtendBitcastSrcVector(DAG, SExtVT, Src, DL)
48004798
: DAG.getNode(ISD::SIGN_EXTEND, DL, SExtVT, Src);
4801-
Opc = UseLASX ? LoongArchISD::XVMSKLTZ : LoongArchISD::VMSKLTZ;
48024799

4803-
SDValue V = DAG.getNode(Opc, DL, MVT::i64, Src);
4800+
SDValue V;
4801+
if (!Subtarget.has32S() || !Subtarget.hasExtLASX()) {
4802+
if (Src.getSimpleValueType() == MVT::v32i8) {
4803+
SDValue Lo, Hi;
4804+
std::tie(Lo, Hi) = DAG.SplitVector(Src, DL);
4805+
Lo = DAG.getNode(LoongArchISD::VMSKLTZ, DL, MVT::i64, Lo);
4806+
Hi = DAG.getNode(LoongArchISD::VMSKLTZ, DL, MVT::i64, Hi);
4807+
Hi = DAG.getNode(ISD::SHL, DL, MVT::i64, Hi,
4808+
DAG.getConstant(16, DL, MVT::i8));
4809+
V = DAG.getNode(ISD::OR, DL, MVT::i64, Lo, Hi);
4810+
} else if (UseLASX) {
4811+
return SDValue();
4812+
}
4813+
}
4814+
4815+
if (!V) {
4816+
Opc = UseLASX ? LoongArchISD::XVMSKLTZ : LoongArchISD::VMSKLTZ;
4817+
V = DAG.getNode(Opc, DL, MVT::i64, Src);
4818+
}
4819+
48044820
EVT T = EVT::getIntegerVT(*DAG.getContext(), SrcVT.getVectorNumElements());
48054821
V = DAG.getZExtOrTrunc(V, DL, T);
48064822
return DAG.getBitcast(VT, V);

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