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[𝘀𝗽𝗿] initial version
Created using spr 1.3.5
2 parents 5d0e26e + e601527 commit 78de99d

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8 files changed

+160
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‎llvm/lib/Target/Sparc/Sparc.td‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,12 @@ def FeatureVIS2
4949
def FeatureVIS3
5050
: SubtargetFeature<"vis3", "IsVIS3", "true",
5151
"Enable Visual Instruction Set extensions III">;
52+
def FeatureUA2005
53+
: SubtargetFeature<"ua2005", "IsUA2005", "true",
54+
"Enable UltraSPARC Architecture 2005 extensions">;
55+
def FeatureUA2007
56+
: SubtargetFeature<"ua2007", "IsUA2007", "true",
57+
"Enable UltraSPARC Architecture 2007 extensions">;
5258
def FeatureLeon
5359
: SubtargetFeature<"leon", "IsLeon", "true",
5460
"Enable LEON extensions">;
@@ -152,13 +158,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
152158
FeatureVIS2],
153159
[TuneSlowRDPC]>;
154160
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
155-
FeatureVIS2]>;
161+
FeatureVIS2, FeatureUA2005]>;
156162
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
157-
FeatureVIS, FeatureVIS2]>;
163+
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
158164
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
159-
FeatureVIS, FeatureVIS2]>;
165+
FeatureVIS, FeatureVIS2, FeatureVIS3,
166+
FeatureUA2005, FeatureUA2007]>;
160167
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
161-
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
168+
FeatureVIS, FeatureVIS2, FeatureVIS3,
169+
FeatureUA2005, FeatureUA2007]>;
162170

163171
// LEON 2 FT generic
164172
def : Processor<"leon2", LEON2Itineraries,

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td‎

Lines changed: 3 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
180180
//===----------------------------------------------------------------------===//
181181

182182
let Predicates = [Is64Bit] in {
183-
184-
def MULXrr : F3_1<2, 0b001001,
185-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
186-
"mulx $rs1, $rs2, $rd",
187-
[(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
188-
def MULXri : F3_2<2, 0b001001,
189-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
190-
"mulx $rs1, $simm13, $rd",
191-
[(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
183+
defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>;
192184

193185
// Division can trap.
194186
let hasSideEffects = 1 in {
195-
def SDIVXrr : F3_1<2, 0b101101,
196-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
197-
"sdivx $rs1, $rs2, $rd",
198-
[(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
199-
def SDIVXri : F3_2<2, 0b101101,
200-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
201-
"sdivx $rs1, $simm13, $rd",
202-
[(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
203-
204-
def UDIVXrr : F3_1<2, 0b001101,
205-
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
206-
"udivx $rs1, $rs2, $rd",
207-
[(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
208-
def UDIVXri : F3_2<2, 0b001101,
209-
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
210-
"udivx $rs1, $simm13, $rd",
211-
[(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
187+
defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>;
188+
defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>;
212189
} // hasSideEffects = 1
213-
214190
} // Predicates = [Is64Bit]
215191

216192

‎llvm/lib/Target/Sparc/SparcInstrFormats.td‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -260,6 +260,23 @@ multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
260260
itin>;
261261
}
262262

263+
// 4-operand instructions.
264+
class F3_4<bits<6> op3val, bits<4> op5val, dag outs, dag ins,
265+
string asmstr, list<dag> pattern = [], InstrItinClass itin = NoItinerary>
266+
: F3<outs, ins, asmstr, pattern, itin> {
267+
bits<4> op5;
268+
bits<5> rs3;
269+
bits<5> rs2;
270+
271+
let op = 2;
272+
let op3 = op3val;
273+
let op5 = op5val;
274+
275+
let Inst{13-9} = rs3;
276+
let Inst{8-5} = op5;
277+
let Inst{4-0} = rs2;
278+
}
279+
263280
class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
264281
InstrItinClass itin = NoItinerary>
265282
: InstSP<outs, ins, asmstr, pattern, itin> {

‎llvm/lib/Target/Sparc/SparcInstrInfo.td‎

Lines changed: 25 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,14 @@ def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
4747
def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
4848
AssemblerPredicate<(all_of FeatureVIS3)>;
4949

50+
// HasUA2005 - This is true when the target processor has UA 2005 extensions.
51+
def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
52+
AssemblerPredicate<(all_of FeatureUA2005)>;
53+
54+
// HasUA2007 - This is true when the target processor has UA 2007 extensions.
55+
def HasUA2007 : Predicate<"Subtarget->isUA2007()">,
56+
AssemblerPredicate<(all_of FeatureUA2007)>;
57+
5058
// HasHardQuad - This is true when the target processor supports quad floating
5159
// point instructions.
5260
def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
@@ -467,22 +475,6 @@ multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
467475
defm A : LoadASI<OpcStr, LoadAOp3Val, RC>;
468476
}
469477

470-
471-
// The LDSTUB instruction is supported for asm only.
472-
// It is unlikely that general-purpose code could make use of it.
473-
// CAS is preferred for sparc v9.
474-
def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
475-
"ldstub [$addr], $rd", []>;
476-
def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
477-
"ldstub [$addr], $rd", []>;
478-
def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
479-
(ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
480-
"ldstuba [$addr] $asi, $rd", []>;
481-
let Predicates = [HasV9], Uses = [ASR3] in
482-
def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
483-
(ins (MEMri $rs1, $simm13):$addr),
484-
"ldstuba [$addr] %asi, $rd", []>;
485-
486478
// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
487479
multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
488480
RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
@@ -740,6 +732,22 @@ let rd = 1, mayStore = 1, Uses = [FSR] in {
740732
"stx %fsr, [$addr]", []>, Requires<[HasV9]>;
741733
}
742734

735+
// B.7. Atomic Load-Store Unsigned Byte Instructions
736+
// (Atomic test-and-set)
737+
// TODO look into the possibility to use this to implment `atomic_flag`.
738+
// If it's possible, then LDSTUB is the preferred way to do it.
739+
def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
740+
"ldstub [$addr], $rd", []>;
741+
def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
742+
"ldstub [$addr], $rd", []>;
743+
def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
744+
(ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
745+
"ldstuba [$addr] $asi, $rd", []>;
746+
let Predicates = [HasV9], Uses = [ASR3] in
747+
def LDSTUBAri : F3_2<3, 0b011101, (outs IntRegs:$rd),
748+
(ins (MEMri $rs1, $simm13):$addr),
749+
"ldstuba [$addr] %asi, $rd", []>;
750+
743751
// Section B.8 - SWAP Register with Memory Instruction
744752
// (Atomic swap)
745753
let Constraints = "$val = $rd" in {
@@ -1968,4 +1976,5 @@ def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
19681976

19691977
include "SparcInstr64Bit.td"
19701978
include "SparcInstrVIS.td"
1979+
include "SparcInstrUAOSA.td"
19711980
include "SparcInstrAliases.td"

‎llvm/lib/Target/Sparc/SparcInstrUAOSA.td‎

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This file contains instruction formats, definitions and patterns needed for
10+
// UA 2005 and UA 2007 instructions on SPARC.
11+
//===----------------------------------------------------------------------===//
12+
13+
// Convenience template for 4-operand instructions
14+
class FourOp<string OpcStr, bits<6> op3val, bits<4> op5val,
15+
RegisterClass RC>
16+
: F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),
17+
!strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
18+
19+
// UltraSPARC Architecture 2005 Instructions
20+
let Predicates = [HasUA2005] in {
21+
let hasSideEffects = 1 in
22+
def ALLCLEAN : InstSP<(outs), (ins), "allclean", []> {
23+
let op = 2;
24+
let Inst{29-19} = 0b00010110001;
25+
let Inst{18-0} = 0;
26+
}
27+
} // Predicates = [HasUA2005]
28+
29+
// UltraSPARC Architecture 2007 Instructions
30+
let Predicates = [HasUA2007] in {
31+
def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
32+
def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
33+
def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
34+
def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
35+
36+
def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
37+
def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
38+
def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
39+
def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
40+
} // Predicates = [HasUA2007]

‎llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005,+ua2007 | FileCheck %s
2+
3+
## UA 2005 instructions.
4+
5+
# CHECK: allclean
6+
0x85,0x88,0x00,0x00
7+
8+
## UA 2007 instructions.
9+
10+
# CHECK: fmadds %f1, %f3, %f5, %f7
11+
0x8f,0xb8,0x4a,0x23
12+
# CHECK: fmaddd %f0, %f2, %f4, %f6
13+
0x8d,0xb8,0x08,0x42
14+
# CHECK: fmsubs %f1, %f3, %f5, %f7
15+
0x8f,0xb8,0x4a,0xa3
16+
# CHECK: fmsubd %f0, %f2, %f4, %f6
17+
0x8d,0xb8,0x08,0xc2
18+
# CHECK: fnmadds %f1, %f3, %f5, %f7
19+
0x8f,0xb8,0x4b,0xa3
20+
# CHECK: fnmaddd %f0, %f2, %f4, %f6
21+
0x8d,0xb8,0x09,0xc2
22+
# CHECK: fnmsubs %f1, %f3, %f5, %f7
23+
0x8f,0xb8,0x4b,0x23
24+
# CHECK: fnmsubd %f0, %f2, %f4, %f6
25+
0x8d,0xb8,0x09,0x42

‎llvm/test/MC/Sparc/sparc-ua2005.s‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2005 --implicit-check-not=error:
2+
! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2005 -show-encoding | FileCheck %s --check-prefixes=UA2005
3+
4+
!! UA 2005 instructions.
5+
6+
! NO-UA2005: error: instruction requires a CPU feature not currently enabled
7+
! UA2005: allclean ! encoding: [0x85,0x88,0x00,0x00]
8+
allclean

‎llvm/test/MC/Sparc/sparc-ua2007.s‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2007 --implicit-check-not=error:
2+
! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2007 -show-encoding | FileCheck %s --check-prefixes=UA2007
3+
4+
!! UA 2007 instructions.
5+
6+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
7+
! UA2007: fmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0x23]
8+
fmadds %f1, %f3, %f5, %f7
9+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
10+
! UA2007: fmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0x42]
11+
fmaddd %f0, %f2, %f4, %f6
12+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
13+
! UA2007: fmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0xa3]
14+
fmsubs %f1, %f3, %f5, %f7
15+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
16+
! UA2007: fmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0xc2]
17+
fmsubd %f0, %f2, %f4, %f6
18+
19+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
20+
! UA2007: fnmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0xa3]
21+
fnmadds %f1, %f3, %f5, %f7
22+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
23+
! UA2007: fnmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0xc2]
24+
fnmaddd %f0, %f2, %f4, %f6
25+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
26+
! UA2007: fnmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0x23]
27+
fnmsubs %f1, %f3, %f5, %f7
28+
! NO-UA2007: error: instruction requires a CPU feature not currently enabled
29+
! UA2007: fnmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0x42]
30+
fnmsubd %f0, %f2, %f4, %f6

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