Skip to content

Commit 78e3ab3

Browse files
tclin914tclin914
committed
[RISCV] Update some tests to use a common check prefix. NFC.
To make it easier to see that the codegen is the same across different options.
1 parent 99a1d5f commit 78e3ab3

File tree

3 files changed

+108
-254
lines changed

3 files changed

+108
-254
lines changed

‎llvm/test/CodeGen/RISCV/rv32xtheadbb.ll‎

Lines changed: 31 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3-
; RUN: | FileCheck %s -check-prefixes=RV32I
3+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
44
; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -verify-machineinstrs < %s \
5-
; RUN: | FileCheck %s -check-prefixes=RV32XTHEADBB,RV32XTHEADBB-NOB
5+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBB,RV32XTHEADBB-NOB
66
; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb,+b -verify-machineinstrs < %s \
7-
; RUN: | FileCheck %s -check-prefixes=RV32XTHEADBB,RV32XTHEADBB-B
7+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBB,RV32XTHEADBB-B
88

99
declare i32 @llvm.ctlz.i32(i32, i1)
1010

@@ -354,57 +354,37 @@ define i32 @sexti1_i32_2(i1 %a) nounwind {
354354

355355
; Make sure we don't use not+th.ext
356356
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
357-
; RV32I-LABEL: sexti1_i32_setcc:
358-
; RV32I: # %bb.0:
359-
; RV32I-NEXT: srli a0, a0, 31
360-
; RV32I-NEXT: addi a0, a0, -1
361-
; RV32I-NEXT: zext.b a0, a0
362-
; RV32I-NEXT: ret
363-
;
364-
; RV32XTHEADBB-LABEL: sexti1_i32_setcc:
365-
; RV32XTHEADBB: # %bb.0:
366-
; RV32XTHEADBB-NEXT: srli a0, a0, 31
367-
; RV32XTHEADBB-NEXT: addi a0, a0, -1
368-
; RV32XTHEADBB-NEXT: zext.b a0, a0
369-
; RV32XTHEADBB-NEXT: ret
357+
; CHECK-LABEL: sexti1_i32_setcc:
358+
; CHECK: # %bb.0:
359+
; CHECK-NEXT: srli a0, a0, 31
360+
; CHECK-NEXT: addi a0, a0, -1
361+
; CHECK-NEXT: zext.b a0, a0
362+
; CHECK-NEXT: ret
370363
%icmp = icmp sgt i32 %a, -1
371364
%sext = sext i1 %icmp to i8
372365
ret i8 %sext
373366
}
374367

375368
; Make sure we don't use seqz+th.ext instead of snez+addi
376369
define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
377-
; RV32I-LABEL: sexti1_i32_setcc_2:
378-
; RV32I: # %bb.0:
379-
; RV32I-NEXT: xor a0, a0, a1
380-
; RV32I-NEXT: snez a0, a0
381-
; RV32I-NEXT: addi a0, a0, -1
382-
; RV32I-NEXT: ret
383-
;
384-
; RV32XTHEADBB-LABEL: sexti1_i32_setcc_2:
385-
; RV32XTHEADBB: # %bb.0:
386-
; RV32XTHEADBB-NEXT: xor a0, a0, a1
387-
; RV32XTHEADBB-NEXT: snez a0, a0
388-
; RV32XTHEADBB-NEXT: addi a0, a0, -1
389-
; RV32XTHEADBB-NEXT: ret
370+
; CHECK-LABEL: sexti1_i32_setcc_2:
371+
; CHECK: # %bb.0:
372+
; CHECK-NEXT: xor a0, a0, a1
373+
; CHECK-NEXT: snez a0, a0
374+
; CHECK-NEXT: addi a0, a0, -1
375+
; CHECK-NEXT: ret
390376
%icmp = icmp eq i32 %a, %b
391377
%sext = sext i1 %icmp to i32
392378
ret i32 %sext
393379
}
394380

395381
; Make sure we don't use th.ext instead of neg.
396382
define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
397-
; RV32I-LABEL: sexti1_i32_setcc_3:
398-
; RV32I: # %bb.0:
399-
; RV32I-NEXT: slt a0, a0, a1
400-
; RV32I-NEXT: neg a0, a0
401-
; RV32I-NEXT: ret
402-
;
403-
; RV32XTHEADBB-LABEL: sexti1_i32_setcc_3:
404-
; RV32XTHEADBB: # %bb.0:
405-
; RV32XTHEADBB-NEXT: slt a0, a0, a1
406-
; RV32XTHEADBB-NEXT: neg a0, a0
407-
; RV32XTHEADBB-NEXT: ret
383+
; CHECK-LABEL: sexti1_i32_setcc_3:
384+
; CHECK: # %bb.0:
385+
; CHECK-NEXT: slt a0, a0, a1
386+
; CHECK-NEXT: neg a0, a0
387+
; CHECK-NEXT: ret
408388
%icmp = icmp slt i32 %a, %b
409389
%sext = sext i1 %icmp to i32
410390
ret i32 %sext
@@ -477,17 +457,11 @@ define i32 @sexth_i32(i32 %a) nounwind {
477457
}
478458

479459
define i32 @no_sexth_i32(i32 %a) nounwind {
480-
; RV32I-LABEL: no_sexth_i32:
481-
; RV32I: # %bb.0:
482-
; RV32I-NEXT: slli a0, a0, 17
483-
; RV32I-NEXT: srai a0, a0, 16
484-
; RV32I-NEXT: ret
485-
;
486-
; RV32XTHEADBB-LABEL: no_sexth_i32:
487-
; RV32XTHEADBB: # %bb.0:
488-
; RV32XTHEADBB-NEXT: slli a0, a0, 17
489-
; RV32XTHEADBB-NEXT: srai a0, a0, 16
490-
; RV32XTHEADBB-NEXT: ret
460+
; CHECK-LABEL: no_sexth_i32:
461+
; CHECK: # %bb.0:
462+
; CHECK-NEXT: slli a0, a0, 17
463+
; CHECK-NEXT: srai a0, a0, 16
464+
; CHECK-NEXT: ret
491465
%shl = shl i32 %a, 17
492466
%shr = ashr exact i32 %shl, 16
493467
ret i32 %shr
@@ -518,19 +492,12 @@ define i64 @sexth_i64(i64 %a) nounwind {
518492
}
519493

520494
define i64 @no_sexth_i64(i64 %a) nounwind {
521-
; RV32I-LABEL: no_sexth_i64:
522-
; RV32I: # %bb.0:
523-
; RV32I-NEXT: slli a1, a0, 17
524-
; RV32I-NEXT: srai a0, a1, 16
525-
; RV32I-NEXT: srai a1, a1, 31
526-
; RV32I-NEXT: ret
527-
;
528-
; RV32XTHEADBB-LABEL: no_sexth_i64:
529-
; RV32XTHEADBB: # %bb.0:
530-
; RV32XTHEADBB-NEXT: slli a1, a0, 17
531-
; RV32XTHEADBB-NEXT: srai a0, a1, 16
532-
; RV32XTHEADBB-NEXT: srai a1, a1, 31
533-
; RV32XTHEADBB-NEXT: ret
495+
; CHECK-LABEL: no_sexth_i64:
496+
; CHECK: # %bb.0:
497+
; CHECK-NEXT: slli a1, a0, 17
498+
; CHECK-NEXT: srai a0, a1, 16
499+
; CHECK-NEXT: srai a1, a1, 31
500+
; CHECK-NEXT: ret
534501
%shl = shl i64 %a, 49
535502
%shr = ashr exact i64 %shl, 48
536503
ret i64 %shr

‎llvm/test/CodeGen/RISCV/rv64xtheadbb.ll‎

Lines changed: 51 additions & 108 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3-
; RUN: | FileCheck %s -check-prefix=RV64I
3+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
44
; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -verify-machineinstrs < %s \
5-
; RUN: | FileCheck %s -check-prefixes=RV64XTHEADBB,RV64XTHEADBB-NOB
5+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64XTHEADBB,RV64XTHEADBB-NOB
66
; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb,+b -verify-machineinstrs < %s \
7-
; RUN: | FileCheck %s -check-prefixes=RV64XTHEADBB,RV64XTHEADBB-B
7+
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64XTHEADBB,RV64XTHEADBB-B
88

99
declare i32 @llvm.ctlz.i32(i32, i1)
1010

@@ -711,57 +711,37 @@ define signext i32 @sexti1_i32_2(i1 %a) nounwind {
711711

712712
; Make sure we don't use not+th.ext
713713
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
714-
; RV64I-LABEL: sexti1_i32_setcc:
715-
; RV64I: # %bb.0:
716-
; RV64I-NEXT: srli a0, a0, 63
717-
; RV64I-NEXT: addi a0, a0, -1
718-
; RV64I-NEXT: zext.b a0, a0
719-
; RV64I-NEXT: ret
720-
;
721-
; RV64XTHEADBB-LABEL: sexti1_i32_setcc:
722-
; RV64XTHEADBB: # %bb.0:
723-
; RV64XTHEADBB-NEXT: srli a0, a0, 63
724-
; RV64XTHEADBB-NEXT: addi a0, a0, -1
725-
; RV64XTHEADBB-NEXT: zext.b a0, a0
726-
; RV64XTHEADBB-NEXT: ret
714+
; CHECK-LABEL: sexti1_i32_setcc:
715+
; CHECK: # %bb.0:
716+
; CHECK-NEXT: srli a0, a0, 63
717+
; CHECK-NEXT: addi a0, a0, -1
718+
; CHECK-NEXT: zext.b a0, a0
719+
; CHECK-NEXT: ret
727720
%icmp = icmp sgt i32 %a, -1
728721
%sext = sext i1 %icmp to i8
729722
ret i8 %sext
730723
}
731724

732725
; Make sure we don't use seqz+th.ext instead of snez+addi
733726
define signext i32 @sexti1_i32_setcc_2(i32 signext %a, i32 signext %b) {
734-
; RV64I-LABEL: sexti1_i32_setcc_2:
735-
; RV64I: # %bb.0:
736-
; RV64I-NEXT: xor a0, a0, a1
737-
; RV64I-NEXT: snez a0, a0
738-
; RV64I-NEXT: addi a0, a0, -1
739-
; RV64I-NEXT: ret
740-
;
741-
; RV64XTHEADBB-LABEL: sexti1_i32_setcc_2:
742-
; RV64XTHEADBB: # %bb.0:
743-
; RV64XTHEADBB-NEXT: xor a0, a0, a1
744-
; RV64XTHEADBB-NEXT: snez a0, a0
745-
; RV64XTHEADBB-NEXT: addi a0, a0, -1
746-
; RV64XTHEADBB-NEXT: ret
727+
; CHECK-LABEL: sexti1_i32_setcc_2:
728+
; CHECK: # %bb.0:
729+
; CHECK-NEXT: xor a0, a0, a1
730+
; CHECK-NEXT: snez a0, a0
731+
; CHECK-NEXT: addi a0, a0, -1
732+
; CHECK-NEXT: ret
747733
%icmp = icmp eq i32 %a, %b
748734
%sext = sext i1 %icmp to i32
749735
ret i32 %sext
750736
}
751737

752738
; Make sure we don't use th.ext instead of neg.
753739
define signext i32 @sexti1_i32_setcc_3(i32 signext %a, i32 signext %b) {
754-
; RV64I-LABEL: sexti1_i32_setcc_3:
755-
; RV64I: # %bb.0:
756-
; RV64I-NEXT: slt a0, a0, a1
757-
; RV64I-NEXT: neg a0, a0
758-
; RV64I-NEXT: ret
759-
;
760-
; RV64XTHEADBB-LABEL: sexti1_i32_setcc_3:
761-
; RV64XTHEADBB: # %bb.0:
762-
; RV64XTHEADBB-NEXT: slt a0, a0, a1
763-
; RV64XTHEADBB-NEXT: neg a0, a0
764-
; RV64XTHEADBB-NEXT: ret
740+
; CHECK-LABEL: sexti1_i32_setcc_3:
741+
; CHECK: # %bb.0:
742+
; CHECK-NEXT: slt a0, a0, a1
743+
; CHECK-NEXT: neg a0, a0
744+
; CHECK-NEXT: ret
765745
%icmp = icmp slt i32 %a, %b
766746
%sext = sext i1 %icmp to i32
767747
ret i32 %sext
@@ -800,57 +780,37 @@ define i64 @sexti1_i64_2(i1 %a) nounwind {
800780

801781
; Make sure we don't use not+th.ext
802782
define zeroext i8 @sexti1_i64_setcc(i64 %a) {
803-
; RV64I-LABEL: sexti1_i64_setcc:
804-
; RV64I: # %bb.0:
805-
; RV64I-NEXT: srli a0, a0, 63
806-
; RV64I-NEXT: addi a0, a0, -1
807-
; RV64I-NEXT: zext.b a0, a0
808-
; RV64I-NEXT: ret
809-
;
810-
; RV64XTHEADBB-LABEL: sexti1_i64_setcc:
811-
; RV64XTHEADBB: # %bb.0:
812-
; RV64XTHEADBB-NEXT: srli a0, a0, 63
813-
; RV64XTHEADBB-NEXT: addi a0, a0, -1
814-
; RV64XTHEADBB-NEXT: zext.b a0, a0
815-
; RV64XTHEADBB-NEXT: ret
783+
; CHECK-LABEL: sexti1_i64_setcc:
784+
; CHECK: # %bb.0:
785+
; CHECK-NEXT: srli a0, a0, 63
786+
; CHECK-NEXT: addi a0, a0, -1
787+
; CHECK-NEXT: zext.b a0, a0
788+
; CHECK-NEXT: ret
816789
%icmp = icmp sgt i64 %a, -1
817790
%sext = sext i1 %icmp to i8
818791
ret i8 %sext
819792
}
820793

821794
; Make sure we don't use seqz+th.ext instead of snez+addi
822795
define i64 @sexti1_i64_setcc_2(i64 %a, i64 %b) {
823-
; RV64I-LABEL: sexti1_i64_setcc_2:
824-
; RV64I: # %bb.0:
825-
; RV64I-NEXT: xor a0, a0, a1
826-
; RV64I-NEXT: snez a0, a0
827-
; RV64I-NEXT: addi a0, a0, -1
828-
; RV64I-NEXT: ret
829-
;
830-
; RV64XTHEADBB-LABEL: sexti1_i64_setcc_2:
831-
; RV64XTHEADBB: # %bb.0:
832-
; RV64XTHEADBB-NEXT: xor a0, a0, a1
833-
; RV64XTHEADBB-NEXT: snez a0, a0
834-
; RV64XTHEADBB-NEXT: addi a0, a0, -1
835-
; RV64XTHEADBB-NEXT: ret
796+
; CHECK-LABEL: sexti1_i64_setcc_2:
797+
; CHECK: # %bb.0:
798+
; CHECK-NEXT: xor a0, a0, a1
799+
; CHECK-NEXT: snez a0, a0
800+
; CHECK-NEXT: addi a0, a0, -1
801+
; CHECK-NEXT: ret
836802
%icmp = icmp eq i64 %a, %b
837803
%sext = sext i1 %icmp to i64
838804
ret i64 %sext
839805
}
840806

841807
; Make sure we don't use th.ext instead of neg.
842808
define i64 @sexti1_i64_setcc_3(i64 %a, i64 %b) {
843-
; RV64I-LABEL: sexti1_i64_setcc_3:
844-
; RV64I: # %bb.0:
845-
; RV64I-NEXT: slt a0, a0, a1
846-
; RV64I-NEXT: neg a0, a0
847-
; RV64I-NEXT: ret
848-
;
849-
; RV64XTHEADBB-LABEL: sexti1_i64_setcc_3:
850-
; RV64XTHEADBB: # %bb.0:
851-
; RV64XTHEADBB-NEXT: slt a0, a0, a1
852-
; RV64XTHEADBB-NEXT: neg a0, a0
853-
; RV64XTHEADBB-NEXT: ret
809+
; CHECK-LABEL: sexti1_i64_setcc_3:
810+
; CHECK: # %bb.0:
811+
; CHECK-NEXT: slt a0, a0, a1
812+
; CHECK-NEXT: neg a0, a0
813+
; CHECK-NEXT: ret
854814
%icmp = icmp slt i64 %a, %b
855815
%sext = sext i1 %icmp to i64
856816
ret i64 %sext
@@ -920,17 +880,11 @@ define signext i32 @sexth_i32(i32 signext %a) nounwind {
920880
}
921881

922882
define signext i32 @no_sexth_i32(i32 signext %a) nounwind {
923-
; RV64I-LABEL: no_sexth_i32:
924-
; RV64I: # %bb.0:
925-
; RV64I-NEXT: slli a0, a0, 49
926-
; RV64I-NEXT: srai a0, a0, 48
927-
; RV64I-NEXT: ret
928-
;
929-
; RV64XTHEADBB-LABEL: no_sexth_i32:
930-
; RV64XTHEADBB: # %bb.0:
931-
; RV64XTHEADBB-NEXT: slli a0, a0, 49
932-
; RV64XTHEADBB-NEXT: srai a0, a0, 48
933-
; RV64XTHEADBB-NEXT: ret
883+
; CHECK-LABEL: no_sexth_i32:
884+
; CHECK: # %bb.0:
885+
; CHECK-NEXT: slli a0, a0, 49
886+
; CHECK-NEXT: srai a0, a0, 48
887+
; CHECK-NEXT: ret
934888
%shl = shl i32 %a, 17
935889
%shr = ashr exact i32 %shl, 16
936890
ret i32 %shr
@@ -958,17 +912,11 @@ define i64 @sexth_i64(i64 %a) nounwind {
958912
}
959913

960914
define i64 @no_sexth_i64(i64 %a) nounwind {
961-
; RV64I-LABEL: no_sexth_i64:
962-
; RV64I: # %bb.0:
963-
; RV64I-NEXT: slli a0, a0, 49
964-
; RV64I-NEXT: srai a0, a0, 48
965-
; RV64I-NEXT: ret
966-
;
967-
; RV64XTHEADBB-LABEL: no_sexth_i64:
968-
; RV64XTHEADBB: # %bb.0:
969-
; RV64XTHEADBB-NEXT: slli a0, a0, 49
970-
; RV64XTHEADBB-NEXT: srai a0, a0, 48
971-
; RV64XTHEADBB-NEXT: ret
915+
; CHECK-LABEL: no_sexth_i64:
916+
; CHECK: # %bb.0:
917+
; CHECK-NEXT: slli a0, a0, 49
918+
; CHECK-NEXT: srai a0, a0, 48
919+
; CHECK-NEXT: ret
972920
%shl = shl i64 %a, 49
973921
%shr = ashr exact i64 %shl, 48
974922
ret i64 %shr
@@ -1067,15 +1015,10 @@ define i64 @zext_bf2_i64(i64 %a) nounwind {
10671015
}
10681016

10691017
define i64 @zext_i64_srliw(i64 %a) nounwind {
1070-
; RV64I-LABEL: zext_i64_srliw:
1071-
; RV64I: # %bb.0:
1072-
; RV64I-NEXT: srliw a0, a0, 16
1073-
; RV64I-NEXT: ret
1074-
;
1075-
; RV64XTHEADBB-LABEL: zext_i64_srliw:
1076-
; RV64XTHEADBB: # %bb.0:
1077-
; RV64XTHEADBB-NEXT: srliw a0, a0, 16
1078-
; RV64XTHEADBB-NEXT: ret
1018+
; CHECK-LABEL: zext_i64_srliw:
1019+
; CHECK: # %bb.0:
1020+
; CHECK-NEXT: srliw a0, a0, 16
1021+
; CHECK-NEXT: ret
10791022
%1 = lshr i64 %a, 16
10801023
%and = and i64 %1, 65535
10811024
ret i64 %and

0 commit comments

Comments
 (0)