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[AMDGPU] Add support for store to constant address space (#153835)
Since we don't stores to the constant address space as IR verifier errors, we need to support their lowering. Fixes SWDEV-499366.
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3 files changed

+189
-11
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -450,7 +450,9 @@ def LoadAddress_constant : AddressSpaceList<[ AddrSpaces.Constant,
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def LoadAddress_global : AddressSpaceList<[ AddrSpaces.Global,
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AddrSpaces.Constant,
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AddrSpaces.Constant32Bit ]>;
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def StoreAddress_global : AddressSpaceList<[ AddrSpaces.Global ]>;
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def StoreAddress_global : AddressSpaceList<[ AddrSpaces.Global,
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AddrSpaces.Constant,
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AddrSpaces.Constant32Bit ]>;
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def LoadAddress_flat : AddressSpaceList<[ AddrSpaces.Flat,
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AddrSpaces.Global,

‎llvm/test/CodeGen/AMDGPU/store-to-constant-error.ll‎

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This file was deleted.

‎llvm/test/CodeGen/AMDGPU/store-to-constant.ll‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,186 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o - | FileCheck %s
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; FIXME: We need to test AS6 but the AS6 variants of the following tests fail because of illegal VGPR to SGPR copy.
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; FIXME: We also want to test memset, memcpy, and memmove, but it needs to fix the SelectionDAG store merging issue (#90714).
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define amdgpu_kernel void @store_as4_i8(ptr addrspace(4) %p, i8 %v) {
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; CHECK-LABEL: store_as4_i8:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_byte v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store i8 %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_i16(ptr addrspace(4) %p, i16 %v) {
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; CHECK-LABEL: store_as4_i16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_short v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store i16 %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_i32(ptr addrspace(4) %p, i32 %v) {
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; CHECK-LABEL: store_as4_i32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store i32 %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_i64(ptr addrspace(4) %p, i64 %v) {
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; CHECK-LABEL: store_as4_i64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v2, s2
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; CHECK-NEXT: v_mov_b32_e32 v3, s3
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; CHECK-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
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; CHECK-NEXT: s_endpgm
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store i64 %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_float(ptr addrspace(4) %p, float %v) {
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; CHECK-LABEL: store_as4_float:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store float %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_double(ptr addrspace(4) %p, double %v) {
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; CHECK-LABEL: store_as4_double:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v2, s2
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; CHECK-NEXT: v_mov_b32_e32 v3, s3
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; CHECK-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]
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; CHECK-NEXT: s_endpgm
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store double %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_half(ptr addrspace(4) %p, half %v) {
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; CHECK-LABEL: store_as4_half:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_short v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store half %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_2xi8(ptr addrspace(4) %p, <2 x i8> %v) {
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; CHECK-LABEL: store_as4_2xi8:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_short v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store <2 x i8> %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_2xi16(ptr addrspace(4) %p, <2 x i16> %v) {
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; CHECK-LABEL: store_as4_2xi16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store <2 x i16> %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_2xi32(ptr addrspace(4) %p, <2 x i32> %v) {
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; CHECK-LABEL: store_as4_2xi32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
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; CHECK-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; CHECK-NEXT: s_endpgm
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store <2 x i32> %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_2xhalf(ptr addrspace(4) %p, <2 x half> %v) {
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; CHECK-LABEL: store_as4_2xhalf:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[8:9], 0x8
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v1, s2
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; CHECK-NEXT: global_store_dword v0, v1, s[0:1]
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; CHECK-NEXT: s_endpgm
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store <2 x half> %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_2xfloat(ptr addrspace(4) %p, <2 x float> %v) {
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; CHECK-LABEL: store_as4_2xfloat:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
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; CHECK-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; CHECK-NEXT: s_endpgm
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store <2 x float> %v, ptr addrspace(4) %p
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ret void
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}
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define amdgpu_kernel void @store_as4_2xdouble(ptr addrspace(4) %p, <2 x double> %v) {
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; CHECK-LABEL: store_as4_2xdouble:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10
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; CHECK-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; CHECK-NEXT: global_store_dwordx4 v4, v[0:3], s[4:5]
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; CHECK-NEXT: s_endpgm
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store <2 x double> %v, ptr addrspace(4) %p
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ret void
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}

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