- Moved the function to SPIRVUtils.cpp

EbinJose2002 · EbinJose2002 · commit 7935c3d70922 · 2025-05-06T14:17:27.000+05:30
- Added Documentation
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
@@ -213,6 +213,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
      - Adds a bitwise instruction on three operands and a look-up table index for specifying the bitwise operation to perform. 
    * - ``SPV_INTEL_subgroup_matrix_multiply_accumulate``
      - Adds an instruction to compute the matrix product of an M x K matrix with a K x N matrix and then add an M x N matrix. 
+   * - ``SPV_INTEL_cluster_attributes``
+     - Adds decorations to indicate the cluster attributes of a function.
 
 To enable multiple extensions, list them separated by comma. For example, to enable support for atomic operations on floating-point numbers and arbitrary precision integers, use:
 
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1980,62 +1980,32 @@ static void handleMIFlagDecoration(MachineInstr &I, const SPIRVSubtarget &ST,
   buildOpDecorate(DstReg, I, TII, SPIRV::Decoration::FPFastMathMode, {FMFlags});
 }
 
-static std::vector<uint32_t>
-getMetaDataValues(std::vector<llvm::MDNode *> &MetaDataList) {
-  std::vector<uint32_t> res;
-  for (auto metaDataNode : MetaDataList) {
-    if (metaDataNode->getNumOperands() > 0) {
-      if (auto *CMD = llvm::dyn_cast<llvm::ConstantAsMetadata>(
-              metaDataNode->getOperand(0))) {
-        if (auto *CI = llvm::dyn_cast<llvm::ConstantInt>(CMD->getValue())) {
-          APInt val = CI->getValue();
-          int64_t decVal = val.getZExtValue();
-          res.push_back(decVal);
-        }
-      }
-    }
-  }
-  return res;
-}
-
-static void handleFunctionDecoration(llvm::Module::const_iterator F,
+static void handleFunctionDecoration(MachineInstr &MI, const SPIRVSubtarget &ST,
                                      const SPIRVInstrInfo &TII,
-                                     MachineModuleInfo *MMI,
-                                     const SPIRVSubtarget &ST) {
-  MachineFunction *MF = MMI->getMachineFunction(*F);
-  Register FuncReg;
-  MachineInstr *FirstInstr = nullptr;
+                                     SPIRV::ModuleAnalysisInfo &MAI,
+                                     llvm::Module::const_iterator F) {
+  Register FuncReg = MI.getOperand(0).getReg();
   llvm::SmallVector<std::pair<unsigned int, llvm::MDNode *>> MetaDataList;
-  // Find function register and first instruction
-  for (auto &MBB : *MF) {
-    for (auto &MI : MBB) {
-      if (MI.getOpcode() == SPIRV::OpFunction) {
-        FirstInstr = &MI;
-        FuncReg = MI.getOperand(0).getReg();
-        break;
-      }
-    }
-    if (FuncReg.isValid() && FirstInstr)
-      break;
-  }
+
   // Add function-level decorations based on metadata
   F->getAllMetadata(MetaDataList);
   for (auto &MetaData : MetaDataList) {
     if (MetaData.second == F->getMetadata("stall_enable") ||
         MetaData.second == F->getMetadata("stall_free")) {
       if (ST.canUseExtension(
               SPIRV::Extension::SPV_INTEL_fpga_cluster_attributes)) {
-        std::vector<llvm::MDNode *> MetaDataVector;
+        llvm::SmallVector<llvm::MDNode *> MetaDataVector;
         MetaDataVector.push_back(MetaData.second);
-        std::vector<uint32_t> params = getMetaDataValues(MetaDataVector);
-        if (params.at(0) == 1) {
-          if (MetaData.second == F->getMetadata("stall_enable")) {
-            buildOpDecorate(FuncReg, *FirstInstr, TII,
+        llvm::SmallVector<uint32_t> params =
+            getConstantFromMetadata(MetaDataVector);
+
+        if (params[0] == 1) {
+          if (MetaData.second == F->getMetadata("stall_enable"))
+            buildOpDecorate(FuncReg, MI, TII,
                             SPIRV::Decoration::StallEnableINTEL, {});
-          } else {
-            buildOpDecorate(FuncReg, *FirstInstr, TII,
-                            SPIRV::Decoration::StallFreeINTEL, {});
-          }
+          else
+            buildOpDecorate(FuncReg, MI, TII, SPIRV::Decoration::StallFreeINTEL,
+                            {});
         }
       }
     }
@@ -2050,11 +2020,13 @@ static void addDecorations(const Module &M, const SPIRVInstrInfo &TII,
     MachineFunction *MF = MMI->getMachineFunction(*F);
     if (!MF)
       continue;
-    for (auto &MBB : *MF)
-      for (auto &MI : MBB)
+    for (auto &MBB : *MF) {
+      for (auto &MI : MBB) {
         handleMIFlagDecoration(MI, ST, TII, MAI.Reqs);
-
-    handleFunctionDecoration(F, TII, MMI, ST);
+        if (MI.getOpcode() == SPIRV::OpFunction)
+          handleFunctionDecoration(MI, ST, TII, MAI, F);
+      }
+    }
   }
 }
 
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -518,7 +518,7 @@ defm FPMaxErrorINTEL : CapabilityOperand<6169, 0, 0, [SPV_INTEL_fp_max_error], [
 defm TernaryBitwiseFunctionINTEL : CapabilityOperand<6241, 0, 0, [SPV_INTEL_ternary_bitwise_function], []>;
 defm SubgroupMatrixMultiplyAccumulateINTEL : CapabilityOperand<6236, 0, 0, [SPV_INTEL_subgroup_matrix_multiply_accumulate], []>;
 defm FPGAClusterAttributesINTEL : CapabilityOperand<5904, 0, 0, [SPV_INTEL_fpga_cluster_attributes], []>;
-defm FPGAClusterAttributesV2INTEL : CapabilityOperand<6150, 0, 0, [SPV_INTEL_fpga_cluster_attributes], []>; 
+defm FPGAClusterAttributesV2INTEL : CapabilityOperand<6150, 0, 0, [SPV_INTEL_fpga_cluster_attributes], []>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define SourceLanguage enum values and at the same time
@@ -1271,7 +1271,7 @@ defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingIN
 defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
 defm FPMaxErrorDecorationINTEL : DecorationOperand<6170, 0, 0, [], [FPMaxErrorINTEL]>;
 defm StallEnableINTEL : DecorationOperand<5905, 0, 0, [SPV_INTEL_fpga_cluster_attributes], [FPGAClusterAttributesINTEL]>;
-defm StallFreeINTEL : DecorationOperand<6151, 0, 0, [SPV_INTEL_fpga_cluster_attributes], [FPGAClusterAttributesV2INTEL]>; 
+defm StallFreeINTEL : DecorationOperand<6151, 0, 0, [SPV_INTEL_fpga_cluster_attributes], [FPGAClusterAttributesV2INTEL]>;
 
 //===----------------------------------------------------------------------===//
 // Multiclass used to define BuiltIn enum values and at the same time
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
@@ -370,6 +370,24 @@ Type *getMDOperandAsType(const MDNode *N, unsigned I) {
   return toTypedPointer(ElementTy);
 }
 
+llvm::SmallVector<uint32_t>
+getConstantFromMetadata(llvm::SmallVector<llvm::MDNode *> &MetaDataList) {
+  llvm::SmallVector<uint32_t> res;
+  for (auto metaDataNode : MetaDataList) {
+    if (metaDataNode->getNumOperands() > 0) {
+      if (auto *CMD = llvm::dyn_cast<llvm::ConstantAsMetadata>(
+              metaDataNode->getOperand(0))) {
+        if (auto *CI = llvm::dyn_cast<llvm::ConstantInt>(CMD->getValue())) {
+          APInt val = CI->getValue();
+          int64_t decVal = val.getZExtValue();
+          res.push_back(decVal);
+        }
+      }
+    }
+  }
+  return res;
+}
+
 // The set of names is borrowed from the SPIR-V translator.
 // TODO: may be implemented in SPIRVBuiltins.td.
 static bool isPipeOrAddressSpaceCastBI(const StringRef MangledName) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h
@@ -243,6 +243,10 @@ bool isSpvIntrinsic(const Value *Arg);
 // Get type of i-th operand of the metadata node.
 Type *getMDOperandAsType(const MDNode *N, unsigned I);
 
+// Extract the constant value from the metadata node.
+llvm::SmallVector<uint32_t>
+getConstantFromMetadata(llvm::SmallVector<llvm::MDNode *> &MetaDataList);
+
 // If OpenCL or SPIR-V builtin function name is recognized, return a demangled
 // name, otherwise return an empty string.
 std::string getOclOrSpirvBuiltinDemangledName(StringRef Name);
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cluster_attributes/cluster_attributes.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_cluster_attributes/cluster_attributes.ll
@@ -1,22 +1,22 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_fpga_cluster_attributes %s -o - | FileCheck %s 
 
-; CHECK-DAG: OpCapability FPGAClusterAttributesINTEL 
-; CHECK-DAG: OpCapability FPGAClusterAttributesV2INTEL 
-; CHECK-DAG: OpExtension "SPV_INTEL_fpga_cluster_attributes" 
-; CHECK-DAG: OpDecorate %[[#STALLENABLE_DEC:]] StallEnableINTEL 
-; CHECK-DAG: OpDecorate %[[#STALLFREE_DEC:]] StallFreeINTEL 
-; CHECK: %[[#STALLENABLE_DEC]] = OpFunction %[[#]] None %[[#]] 
-; CHECK: %[[#STALLFREE_DEC]] = OpFunction %[[#]] None %[[#]] 
+; CHECK-DAG: OpCapability FPGAClusterAttributesINTEL
+; CHECK-DAG: OpCapability FPGAClusterAttributesV2INTEL
+; CHECK-DAG: OpExtension "SPV_INTEL_fpga_cluster_attributes"
+; CHECK-DAG: OpDecorate %[[#STALLENABLE_DEC:]] StallEnableINTEL
+; CHECK-DAG: OpDecorate %[[#STALLFREE_DEC:]] StallFreeINTEL
+; CHECK: %[[#STALLENABLE_DEC]] = OpFunction %[[#]] None %[[#]]
+; CHECK: %[[#STALLFREE_DEC]] = OpFunction %[[#]] None %[[#]]
 
 define spir_func void @test_fpga_stallenable_attr() !stall_enable !0 {
    entry:
     ret void
-} 
+}
 
 define spir_func void @test_fpga_stallfree_attr() !stall_free !1 {
    entry:
     ret void
-} 
+}
 
-!0 = !{ i32 1 } 
-!1 = !{ i32 1 } 
+!0 = !{ i32 1 }
+!1 = !{ i32 1 }
