Made the following changes like

ukalappa-mips · ukalappa-mips · commit 7962538724d5 · 2025-06-26T12:19:41.000Z
a)Refactored the code for proper indent with clang format.
  b)Emit ADDI for 11 bits unsigned immediate offset .
  c)Removed the DecodeSImm definition (not used).
  d)Updated the testcase.
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1527,7 +1527,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidUImm9:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, 0, (1 << 9) - 1,
-        "immediate must be a multiple of 9 bytes in the range");
+        "immediate offset must be in the range[0-511]");
   case Match_InvalidBareSImm9Lsb0:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -535,19 +535,6 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
-template <int Bits>
-static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
-                               const MCDisassembler *Decoder) {
-  if (Imm & ~((1LL << Bits) - 1))
-    return MCDisassembler::Fail;
-
-  // Imm is a signed immediate, so sign extend it.
-  if (Imm & (1 << (Bits - 1)))
-    Imm |= ~((1LL << Bits) - 1);
-
-  Inst.addOperand(MCOperand::createImm(Imm));
-  return MCDisassembler::Success;
-}
 
 static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
                                                uint64_t Address,
@@ -589,9 +576,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
 static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
                                         uint64_t Address,
                                         const MCDisassembler *Decoder);
-template <int Bits>
-static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
-                               const MCDisassembler *Decoder);
 
 #include "RISCVGenDisassemblerTables.inc"
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2926,7 +2926,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
 }
 
 /// Similar to SelectAddrRegImm, except that the offset restricted for
-/// nine bits.
+/// unsinged nine bits.
 bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
                                           SDValue &Offset) {
   if (SelectAddrFrameIndex(Addr, Base, Offset))
@@ -2936,7 +2936,6 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
   MVT VT = Addr.getSimpleValueType();
 
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
-
     int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
     if (isUInt<9>(CVal)) {
       Base = Addr.getOperand(0);
@@ -2947,13 +2946,13 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
       return true;
     }
 
-    // Handle with 12 bit ofset  immediates with ADDI.
+    // Handle with 12 bit offset with sign bit off with ADDI.
+    // For Immediate Range [0, 2047]
     else if (Addr.getOpcode() == ISD::ADD &&
              isa<ConstantSDNode>(Addr.getOperand(1))) {
-      int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
       assert(!isUInt<9>(CVal) && "uimm9 not already handled?");
 
-      if (isUInt<12>(CVal)) {
+      if (isUInt<11>(CVal)) {
         Base = SDValue(CurDAG->getMachineNode(
                            RISCV::ADDI, DL, VT, Addr.getOperand(0),
                            CurDAG->getSignedTargetConstant(CVal, DL, VT)),
@@ -2963,10 +2962,6 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
       }
     }
   }
-  // Immediates more than 12 bits i.e LUI,ADDI,ADD
-  if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr, Base, Offset,
-                         /*IsPrefetch=*/true))
-    return true;
 
   Base = Addr;
   Offset = CurDAG->getTargetConstant(0, DL, VT);
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -45,9 +45,6 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
                                     InlineAsm::ConstraintCode ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 
-  bool SelectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
-                                  unsigned OffsetBits,
-                                  unsigned ShiftAmount);
   bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
   bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
   bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
@@ -110,39 +110,39 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
 }
 
 // Prefetch format.
-let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
 class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<9> imm9;
   bits<5> rs1;
   bits<5> hint;
 
-  let Inst{31 - 29} = 0b000;
-  let Inst{28 - 20} = imm9{8 - 0};
-  let Inst{19 - 15} = rs1;
-  let Inst{14 - 12} = 0b000;
-  let Inst{11 - 7} = hint;
-  let Inst{6 - 0} = OPC_CUSTOM_0.Value;
+  let Inst{31-29} = 0b000;
+  let Inst{28-20} = imm9;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = 0b000;
+  let Inst{11-7} = hint;
+  let Inst{6-0} = OPC_CUSTOM_0.Value;
 }
 
 //===----------------------------------------------------------------------===//
 // MIPS extensions
 //===----------------------------------------------------------------------===//
 let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
-  def MIPSPREFETCH : Mips_prefetch_ri<(outs),(ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
-                                        "mips.perf", "$hint, ${imm9}(${rs1})">,
+  def MIPS_PREFETCH : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
+                                        "mips.pref", "$hint, ${imm9}(${rs1})">,
                        Sched<[]>;
 }
 
 let Predicates = [HasVendorXMIPSCBOP] in {
   // Prefetch Data Write.
-  def : Pat<(prefetch(AddrRegImm9(XLenVT GPR:$rs1),uimm9:$imm9),
+  def : Pat<(prefetch (AddrRegImm9  (XLenVT GPR:$rs1), uimm9:$imm9),
              (i32 1), timm, (i32 1)),
-            (MIPSPREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
+            (MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
   // Prefetch Data Read.
-  def : Pat<(prefetch(AddrRegImm9(XLenVT GPR:$rs1),uimm9:$imm9),
+  def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
              (i32 0), timm, (i32 1)),
-            (MIPSPREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
+            (MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
 }
 
 let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
@@ -1,40 +1,32 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
 ; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
 
-define dso_local void @prefetch_read(ptr noundef %a) {
+define void @prefetch_read(ptr noundef %ptr) nounwind {
 ; RV32XMIPSPREFETCH-LABEL: prefetch_read:
-; RV32XMIPSPREFETCH:    mips.perf       8, 511(a0)
+; RV32XMIPSPREFETCH:    mips.pref       8, 1(a0)
 ;
 ; RV64XMIPSPREFETCH-LABEL: prefetch_read:
-; RV64XMIPSPREFETCH:    mips.perf       8, 511(a0)
+; RV64XMIPSPREFETCH:    mips.pref       8, 1(a0)
 entry:
-  %a.addr = alloca ptr, align 8
-  store ptr %a, ptr %a.addr, align 8
-  %0 = load ptr, ptr %a.addr, align 8
-  %arrayidx = getelementptr inbounds i8, ptr %0, i64 511
-  call void @llvm.prefetch.p0(ptr %arrayidx, i32 0, i32 0, i32 1)
+  %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 1
+  tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 1)
+  ret void
   ret void
 }
-
-declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg, i32 immarg, i32 immarg) 
-
-define dso_local void @prefetch_write(ptr noundef %a)  {
-entry:
+ 
+define void @prefetch_write(ptr noundef %ptr) nounwind  {
 ; RV32XMIPSPREFETCH-LABEL: prefetch_write:
-; RV32XMIPSPREFETCH:         addi    a1, a0, 512  
-; RV32XMIPSPREFETCH-NEXT:    mips.perf       9, 0(a1)
+; RV32XMIPSPREFETCH:         addi    a0, a0, 512  
+; RV32XMIPSPREFETCH-NEXT:    mips.pref       9, 0(a0)
 ;
 ; RV64XMIPSPREFETCH-LABEL: prefetch_write:
-; RV64XMIPSPREFETCH:         addi    a1, a0, 512 
-; RV64XMIPSPREFETCH-NEXT:    mips.perf       9, 0(a1)
-  %a.addr = alloca ptr, align 8
-  store ptr %a, ptr %a.addr, align 8
-  %0 = load ptr, ptr %a.addr, align 8
-  %arrayidx = getelementptr inbounds i8, ptr %0, i64 512
-  call void @llvm.prefetch.p0(ptr %arrayidx, i32 1, i32 0, i32 1)
+; RV64XMIPSPREFETCH:         addi    a0, a0, 512 
+; RV64XMIPSPREFETCH-NEXT:    mips.pref       9, 0(a0)
+entry:
+  %arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 512
+  tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 1, i32 0, i32 1)
   ret void
 }
 
diff --git a/llvm/test/MC/RISCV/xmips-invalid.s b/llvm/test/MC/RISCV/xmips-invalid.s
@@ -1,13 +1,13 @@
 # RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
 # RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipsbcop < %s 2>&1 | FileCheck %s
 
-mips.perf   8, 512(a0)
+mips.pref   8, 512(a0)
 # CHECK: error: invalid operand for instruction
 
-mips.perf	8
+mips.pref	8
 # CHECK: error: too few operands for instruction
 
-mips.perf	8, 511(a0)
+mips.pref	8, 511(a0)
 # CHECK-FEATURE: error: instruction requires the following: 'Xmipscbop' (MIPS hardware prefetch)
 
 mips.ccmov x0, x1, 0x10
diff --git a/llvm/test/MC/RISCV/xmips-valid.s b/llvm/test/MC/RISCV/xmips-valid.s
@@ -4,15 +4,15 @@
 # RUN:   | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -d - \
 # RUN:   | FileCheck -check-prefix=CHECK-DIS %s
 
-# CHECK-INST: mips.perf	8, 511(a0)
+# CHECK-INST: mips.pref 8, 511(a0)
 # CHECK-ENC:  encoding: [0x0b,0x04,0xf5,0x1f]
-mips.perf	8, 511(a0)
+mips.pref	8, 511(a0)
 
 # CHECK-DIS: mips.perf 0x8, 0x1ff(a0)
 
-# CHECK-INST: mips.perf	9, 0(a0)
+# CHECK-INST: mips.pref 9, 0(a0)
 # CHECK-ENC:  encoding: [0x8b,0x04,0x05,0x00]
-mips.perf	9, 0(a0)
+mips.pref	9, 0(a0)
 
 # CHECK-DIS: mips.perf 0x9, 0x0(a0)
 
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1140,9 +1140,9 @@ R"(All available -march extensions for RISC-V
     xcvmac               1.0
     xcvmem               1.0
     xcvsimd              1.0
+    xmipscbop            1.0
     xmipscmov            1.0
     xmipslsp             1.0
-    xmipscbop            1.0
     xsfcease             1.0
     xsfmm128t            0.6
     xsfmm16t             0.6
