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topperctopperc
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fixup! Add end to end tests.
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‎llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s --check-prefix=RV32I
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; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s --check-prefix=RV64I
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define i8 @scmp.8.8(i8 signext %x, i8 signext %y) nounwind {
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; RV32I-LABEL: scmp.8.8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: blt a1, a0, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: blt a2, a1, .LBB0_3
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; RV32I-NEXT: j .LBB0_4
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: bge a2, a1, .LBB0_4
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; RV32I-NEXT: .LBB0_3:
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; RV32I-NEXT: li a0, -1
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; RV32I-NEXT: .LBB0_4:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: scmp.8.8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: blt a1, a0, .LBB0_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: blt a2, a1, .LBB0_3
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; RV64I-NEXT: j .LBB0_4
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; RV64I-NEXT: .LBB0_2:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: bge a2, a1, .LBB0_4
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; RV64I-NEXT: .LBB0_3:
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; RV64I-NEXT: li a0, -1
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; RV64I-NEXT: .LBB0_4:
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @scmp.8.16(i16 signext %x, i16 signext %y) nounwind {
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; RV32I-LABEL: scmp.8.16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: blt a1, a0, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: blt a2, a1, .LBB1_3
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; RV32I-NEXT: j .LBB1_4
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: bge a2, a1, .LBB1_4
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; RV32I-NEXT: .LBB1_3:
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; RV32I-NEXT: li a0, -1
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; RV32I-NEXT: .LBB1_4:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: scmp.8.16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: blt a1, a0, .LBB1_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: blt a2, a1, .LBB1_3
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; RV64I-NEXT: j .LBB1_4
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; RV64I-NEXT: .LBB1_2:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: bge a2, a1, .LBB1_4
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; RV64I-NEXT: .LBB1_3:
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; RV64I-NEXT: li a0, -1
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; RV64I-NEXT: .LBB1_4:
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: scmp.8.32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: blt a1, a0, .LBB2_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: blt a2, a1, .LBB2_3
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; RV32I-NEXT: j .LBB2_4
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: bge a2, a1, .LBB2_4
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; RV32I-NEXT: .LBB2_3:
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; RV32I-NEXT: li a0, -1
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; RV32I-NEXT: .LBB2_4:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: scmp.8.32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a2, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: blt a1, a2, .LBB2_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: blt a2, a1, .LBB2_3
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; RV64I-NEXT: j .LBB2_4
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; RV64I-NEXT: .LBB2_2:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: bge a2, a1, .LBB2_4
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; RV64I-NEXT: .LBB2_3:
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; RV64I-NEXT: li a0, -1
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; RV64I-NEXT: .LBB2_4:
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.scmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: scmp.8.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: slt a4, a3, a1
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; RV32I-NEXT: bnez a4, .LBB3_3
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; RV32I-NEXT: j .LBB3_4
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: sltu a4, a2, a0
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; RV32I-NEXT: beqz a4, .LBB3_4
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; RV32I-NEXT: .LBB3_3:
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; RV32I-NEXT: li a4, 1
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; RV32I-NEXT: .LBB3_4:
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; RV32I-NEXT: beq a1, a3, .LBB3_6
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; RV32I-NEXT: # %bb.5:
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; RV32I-NEXT: slt a0, a1, a3
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; RV32I-NEXT: bnez a0, .LBB3_7
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; RV32I-NEXT: j .LBB3_8
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; RV32I-NEXT: .LBB3_6:
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; RV32I-NEXT: sltu a0, a0, a2
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; RV32I-NEXT: beqz a0, .LBB3_8
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; RV32I-NEXT: .LBB3_7:
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; RV32I-NEXT: li a4, -1
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; RV32I-NEXT: .LBB3_8:
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; RV32I-NEXT: mv a0, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: scmp.8.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: blt a1, a0, .LBB3_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: blt a2, a1, .LBB3_3
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; RV64I-NEXT: j .LBB3_4
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; RV64I-NEXT: .LBB3_2:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: bge a2, a1, .LBB3_4
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; RV64I-NEXT: .LBB3_3:
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; RV64I-NEXT: li a0, -1
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; RV64I-NEXT: .LBB3_4:
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; RV64I-NEXT: ret
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%1 = call i8 @llvm.scmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: scmp.32.32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: blt a1, a0, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a0, 0
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; RV32I-NEXT: blt a2, a1, .LBB4_3
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; RV32I-NEXT: j .LBB4_4
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: bge a2, a1, .LBB4_4
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; RV32I-NEXT: .LBB4_3:
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; RV32I-NEXT: li a0, -1
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; RV32I-NEXT: .LBB4_4:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: scmp.32.32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a2, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: blt a1, a2, .LBB4_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: blt a2, a1, .LBB4_3
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; RV64I-NEXT: j .LBB4_4
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: bge a2, a1, .LBB4_4
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; RV64I-NEXT: .LBB4_3:
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; RV64I-NEXT: li a0, -1
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; RV64I-NEXT: .LBB4_4:
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.scmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: scmp.32.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beq a1, a3, .LBB5_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: slt a4, a3, a1
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; RV32I-NEXT: bnez a4, .LBB5_3
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; RV32I-NEXT: j .LBB5_4
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; RV32I-NEXT: .LBB5_2:
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; RV32I-NEXT: sltu a4, a2, a0
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; RV32I-NEXT: beqz a4, .LBB5_4
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; RV32I-NEXT: .LBB5_3:
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; RV32I-NEXT: li a4, 1
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; RV32I-NEXT: .LBB5_4:
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; RV32I-NEXT: beq a1, a3, .LBB5_6
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; RV32I-NEXT: # %bb.5:
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; RV32I-NEXT: slt a0, a1, a3
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; RV32I-NEXT: bnez a0, .LBB5_7
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; RV32I-NEXT: j .LBB5_8
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; RV32I-NEXT: .LBB5_6:
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; RV32I-NEXT: sltu a0, a0, a2
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; RV32I-NEXT: beqz a0, .LBB5_8
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; RV32I-NEXT: .LBB5_7:
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; RV32I-NEXT: li a4, -1
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; RV32I-NEXT: .LBB5_8:
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; RV32I-NEXT: mv a0, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: scmp.32.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: blt a1, a0, .LBB5_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: blt a2, a1, .LBB5_3
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; RV64I-NEXT: j .LBB5_4
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; RV64I-NEXT: .LBB5_2:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: bge a2, a1, .LBB5_4
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; RV64I-NEXT: .LBB5_3:
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; RV64I-NEXT: li a0, -1
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; RV64I-NEXT: .LBB5_4:
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; RV64I-NEXT: ret
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%1 = call i32 @llvm.scmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: scmp.64.64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a4, a0
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; RV32I-NEXT: beq a1, a3, .LBB6_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: slt a0, a3, a1
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; RV32I-NEXT: bnez a0, .LBB6_3
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; RV32I-NEXT: j .LBB6_4
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; RV32I-NEXT: .LBB6_2:
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; RV32I-NEXT: sltu a0, a2, a4
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; RV32I-NEXT: beqz a0, .LBB6_4
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; RV32I-NEXT: .LBB6_3:
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: .LBB6_4:
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; RV32I-NEXT: beq a1, a3, .LBB6_6
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; RV32I-NEXT: # %bb.5:
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; RV32I-NEXT: slt a1, a1, a3
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; RV32I-NEXT: bnez a1, .LBB6_7
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; RV32I-NEXT: j .LBB6_8
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; RV32I-NEXT: .LBB6_6:
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; RV32I-NEXT: sltu a1, a4, a2
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; RV32I-NEXT: beqz a1, .LBB6_8
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; RV32I-NEXT: .LBB6_7:
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; RV32I-NEXT: li a0, -1
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; RV32I-NEXT: li a1, -1
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; RV32I-NEXT: .LBB6_8:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: scmp.64.64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a2, a0
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; RV64I-NEXT: blt a1, a0, .LBB6_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 0
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; RV64I-NEXT: blt a2, a1, .LBB6_3
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; RV64I-NEXT: j .LBB6_4
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; RV64I-NEXT: .LBB6_2:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: bge a2, a1, .LBB6_4
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; RV64I-NEXT: .LBB6_3:
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; RV64I-NEXT: li a0, -1
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; RV64I-NEXT: .LBB6_4:
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; RV64I-NEXT: ret
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%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
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ret i64 %1
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}

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