wip

Signed-off-by: Mikhail R. Gadelha <[email protected]>

Author: mikhailramalho

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -2542,6 +2542,10 @@ class TargetLoweringBase {
   /// type and indicate what to do about it. Note that VT may refer to either
   /// the type of a result or that of an operand of Op.
   void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) {
+    // if(Op == ISD::VECREDUCE_FADD && VT == MVT::nxv1f16)
+    //   asm("int $3");
+    // if(Op == ISD::VECREDUCE_FADD && VT == MVT::nxv1f32)
+    //   asm("int $3");
     assert(Op < std::size(OpActions[0]) && "Table isn't big enough!");
     OpActions[(unsigned)VT.SimpleTy][Op] = Action;
   }

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

@@ -5154,6 +5154,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
       Node->getOpcode() == ISD::VP_REDUCE_FMINIMUM ||
       Node->getOpcode() == ISD::VP_REDUCE_SEQ_FADD)
     OVT = Node->getOperand(1).getSimpleValueType();
+  if (Node->getOpcode() == ISD::VECREDUCE_FADD)
+    OVT = Node->getOperand(0).getSimpleValueType();
   if (Node->getOpcode() == ISD::BR_CC ||
       Node->getOpcode() == ISD::SELECT_CC)
     OVT = Node->getOperand(2).getSimpleValueType();
@@ -5854,6 +5856,23 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
                     DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)));
     break;
   }
+  case ISD::VECREDUCE_ADD:
+  case ISD::VECREDUCE_MUL:
+  case ISD::VECREDUCE_AND:
+  case ISD::VECREDUCE_OR:
+  case ISD::VECREDUCE_XOR:
+  case ISD::VECREDUCE_SMAX:
+  case ISD::VECREDUCE_SMIN:
+  case ISD::VECREDUCE_UMAX:
+  case ISD::VECREDUCE_UMIN:
+  case ISD::VECREDUCE_FADD:
+  case ISD::VECREDUCE_FMUL:
+  case ISD::VECREDUCE_FMAX:
+  case ISD::VECREDUCE_FMIN:
+  case ISD::VECREDUCE_FMAXIMUM:
+  case ISD::VECREDUCE_FMINIMUM:
+    Results.push_back(TLI.expandVecReduce(Node, DAG));
+    break;
   case ISD::VP_REDUCE_FADD:
   case ISD::VP_REDUCE_FMUL:
   case ISD::VP_REDUCE_FMAX:

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

@@ -1003,6 +1003,11 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
   LLVM_DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG));
   SDValue Res = SDValue();
 
+  // if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
+  //   LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
+  //   return false;
+  // }
+
   switch (N->getOpcode()) {
   default:
 #ifndef NDEBUG

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

@@ -538,6 +538,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
   }
 
   LLVM_DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG));
+  if (Node->getOpcode() == ISD::VECREDUCE_FADD)
+      Action = TargetLowering::Legal;
 
   SmallVector<SDValue, 8> ResultVals;
   switch (Action) {
@@ -1152,23 +1154,6 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
 #include "llvm/IR/ConstrainedOps.def"
     ExpandStrictFPOp(Node, Results);
     return;
-  case ISD::VECREDUCE_ADD:
-  case ISD::VECREDUCE_MUL:
-  case ISD::VECREDUCE_AND:
-  case ISD::VECREDUCE_OR:
-  case ISD::VECREDUCE_XOR:
-  case ISD::VECREDUCE_SMAX:
-  case ISD::VECREDUCE_SMIN:
-  case ISD::VECREDUCE_UMAX:
-  case ISD::VECREDUCE_UMIN:
-  case ISD::VECREDUCE_FADD:
-  case ISD::VECREDUCE_FMUL:
-  case ISD::VECREDUCE_FMAX:
-  case ISD::VECREDUCE_FMIN:
-  case ISD::VECREDUCE_FMAXIMUM:
-  case ISD::VECREDUCE_FMINIMUM:
-    Results.push_back(TLI.expandVecReduce(Node, DAG));
-    return;
   case ISD::VECREDUCE_SEQ_FADD:
   case ISD::VECREDUCE_SEQ_FMUL:
     Results.push_back(TLI.expandVecReduceSeq(Node, DAG));

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -587,6 +587,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f64, Expand);
   }
 
+  // for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16,
+  //                 ISD::STRICT_FP_TO_FP16}) {
+  //   setOperationAction(Op, MVT::f128, Custom);
+  // }
+
   if (Subtarget.is64Bit()) {
     setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT,
                         ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
@@ -975,7 +980,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         ISD::VP_FMINIMUM,
         ISD::VP_FMAXIMUM,
         ISD::VP_REDUCE_FMINIMUM,
-        ISD::VP_REDUCE_FMAXIMUM};
+        ISD::VP_REDUCE_FMAXIMUM,
+        ISD::VECREDUCE_FADD};
 
     // Sets common operation actions on RVV floating-point vector types.
     const auto SetCommonVFPActions = [&](MVT VT) {