1313#include " AArch64MachineFunctionInfo.h"
1414#include " AArch64TargetMachine.h"
1515#include " MCTargetDesc/AArch64AddressingModes.h"
16+ #include " MCTargetDesc/AArch64MCTargetDesc.h"
1617#include " llvm/ADT/APSInt.h"
1718#include " llvm/CodeGen/ISDOpcodes.h"
1819#include " llvm/CodeGen/SelectionDAGISel.h"
@@ -4558,9 +4559,15 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
45584559 !TLI->isAllActivePredicate (*CurDAG, N1.getOperand (0 )))
45594560 return false ;
45604561
4561- SDValue XOR = N0.getOperand (1 );
4562- if (XOR.getOpcode () != ISD::XOR || XOR != N1.getOperand (1 ))
4563- return false ;
4562+ SDValue R1, R2;
4563+ if (N0.getOperand (1 ).getOpcode () != ISD::XOR) {
4564+ if (N0.getOperand (1 ) != N1.getOperand (1 ))
4565+ return false ;
4566+ SDLoc DL (N1->getOperand (0 ));
4567+ SDValue Zero = CurDAG->getRegister (AArch64::XZR, N1->getOperand (0 ).getValueType ());
4568+ R1 = N1->getOperand (0 );
4569+ R2 = Zero;
4570+ }
45644571
45654572 APInt ShlAmt, ShrAmt;
45664573 if (!ISD::isConstantSplatVector (N0.getOperand (2 ).getNode (), ShlAmt) ||
@@ -4574,7 +4581,7 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
45744581 SDValue Imm =
45754582 CurDAG->getTargetConstant (ShrAmt.getZExtValue (), DL, MVT::i32 );
45764583
4577- SDValue Ops[] = {XOR. getOperand ( 0 ), XOR. getOperand ( 1 ) , Imm};
4584+ SDValue Ops[] = {R1, R2 , Imm};
45784585 if (auto Opc = SelectOpcodeFromVT<SelectTypeKind::Int>(
45794586 VT, {AArch64::XAR_ZZZI_B, AArch64::XAR_ZZZI_H, AArch64::XAR_ZZZI_S,
45804587 AArch64::XAR_ZZZI_D})) {
@@ -4591,13 +4598,21 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
45914598 N1->getOpcode () != AArch64ISD::VLSHR)
45924599 return false ;
45934600
4594- if (N0-> getOperand ( 0 ) != N1-> getOperand ( 0 ) ||
4595- N1 ->getOperand (0 )-> getOpcode () != ISD::XOR )
4601+
4602+ if (N0 ->getOperand (0 ) != N1-> getOperand ( 0 ) )
45964603 return false ;
45974604
4598- SDValue XOR = N0.getOperand (0 );
4599- SDValue R1 = XOR.getOperand (0 );
4600- SDValue R2 = XOR.getOperand (1 );
4605+ SDValue R1, R2;
4606+ if (N1->getOperand (0 )->getOpcode () != ISD::XOR) {
4607+ SDLoc DL (N1->getOperand (0 ));
4608+ SDValue Zero = CurDAG->getRegister (AArch64::XZR, N1->getOperand (0 ).getValueType ());
4609+ R1 = N1->getOperand (0 );
4610+ R2 = Zero;
4611+ } else {
4612+ SDValue XOR = N0.getOperand (0 );
4613+ R1 = XOR.getOperand (0 );
4614+ R2 = XOR.getOperand (1 );
4615+ }
46014616
46024617 unsigned HsAmt = N0.getConstantOperandVal (1 );
46034618 unsigned ShAmt = N1.getConstantOperandVal (1 );
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