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Register missing SDNodes in TableGen
This also removes some unused SDNodes (rather than add the definitions)
1 parent 79d9c06 commit 7a1e2e5

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3 files changed

+80
-143
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3 files changed

+80
-143
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 79 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1044,6 +1044,19 @@ def AArch64mrs : SDNode<"AArch64ISD::MRS",
10441044
SDTCisVT<2, i32>]>,
10451045
[SDNPHasChain]>;
10461046

1047+
// 128-bit system register accesses
1048+
// lo64, hi64, chain = MRRS(chain, sysregname)
1049+
def AArch64mrrs : SDNode<"AArch64ISD::MRRS",
1050+
SDTypeProfile<2, 1, [SDTCisVT<0, i64>,
1051+
SDTCisVT<1, i64>]>,
1052+
[SDNPHasChain]>;
1053+
1054+
// chain = MSRR(chain, sysregname, lo64, hi64)
1055+
def AArch64msrr : SDNode<"AArch64ISD::MSRR",
1056+
SDTypeProfile<0, 3, [SDTCisVT<1, i64>,
1057+
SDTCisVT<2, i64>]>,
1058+
[SDNPHasChain]>;
1059+
10471060
def SD_AArch64rshrnb : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisInt<2>]>;
10481061
def AArch64rshrnb : SDNode<"AArch64ISD::RSHRNB_I", SD_AArch64rshrnb>;
10491062
def AArch64rshrnb_pf : PatFrags<(ops node:$rs, node:$i),
@@ -1053,6 +1066,66 @@ def AArch64rshrnb_pf : PatFrags<(ops node:$rs, node:$i),
10531066
def AArch64CttzElts : SDNode<"AArch64ISD::CTTZ_ELTS", SDTypeProfile<1, 1,
10541067
[SDTCisInt<0>, SDTCisVec<1>]>, []>;
10551068

1069+
def AArch64ld2post : SDNode<"AArch64ISD::LD2post", SDTypeProfile<3, 2, []>, [
1070+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1071+
def AArch64ld3post : SDNode<"AArch64ISD::LD3post", SDTypeProfile<4, 2, []>, [
1072+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1073+
def AArch64ld4post : SDNode<"AArch64ISD::LD4post", SDTypeProfile<5, 2, []>, [
1074+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1075+
def AArch64st2post : SDNode<"AArch64ISD::ST2post", SDTypeProfile<1, 4, []>, [
1076+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1077+
def AArch64st3post : SDNode<"AArch64ISD::ST3post", SDTypeProfile<1, 5, []>, [
1078+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1079+
def AArch64st4post : SDNode<"AArch64ISD::ST4post", SDTypeProfile<1, 6, []>, [
1080+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1081+
def AArch64ld1x2post : SDNode<"AArch64ISD::LD1x2post", SDTypeProfile<3, 2, []>, [
1082+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1083+
def AArch64ld1x3post : SDNode<"AArch64ISD::LD1x3post", SDTypeProfile<4, 2, []>, [
1084+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1085+
def AArch64ld1x4post : SDNode<"AArch64ISD::LD1x4post", SDTypeProfile<5, 2, []>, [
1086+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1087+
def AArch64st1x2post : SDNode<"AArch64ISD::ST1x2post", SDTypeProfile<1, 4, []>, [
1088+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1089+
def AArch64st1x3post : SDNode<"AArch64ISD::ST1x3post", SDTypeProfile<1, 5, []>, [
1090+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1091+
def AArch64st1x4post : SDNode<"AArch64ISD::ST1x4post", SDTypeProfile<1, 6, []>, [
1092+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1093+
def AArch64ld1duppost : SDNode<"AArch64ISD::LD1DUPpost", SDTypeProfile<2, 2, []>, [
1094+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1095+
def AArch64ld2duppost : SDNode<"AArch64ISD::LD2DUPpost", SDTypeProfile<3, 2, []>, [
1096+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1097+
def AArch64ld3duppost: SDNode<"AArch64ISD::LD3DUPpost", SDTypeProfile<4, 2, []>, [
1098+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1099+
def AArch64ld4duppost: SDNode<"AArch64ISD::LD4DUPpost", SDTypeProfile<5, 2, []>, [
1100+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1101+
def AArch64ld1lanepost: SDNode<"AArch64ISD::LD1LANEpost", SDTypeProfile<2, 4, []>, [
1102+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1103+
def AArch64ld2lanepost : SDNode<"AArch64ISD::LD2LANEpost", SDTypeProfile<3, 5, []>, [
1104+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1105+
def AArch64ld3lanepost: SDNode<"AArch64ISD::LD3LANEpost", SDTypeProfile<4, 6, []>, [
1106+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1107+
def AArch64ld4lanepost: SDNode<"AArch64ISD::LD4LANEpost", SDTypeProfile<5, 7, []>, [
1108+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1109+
def AArch64st2lanepost : SDNode<"AArch64ISD::ST2LANEpost", SDTypeProfile<1, 5, []>, [
1110+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1111+
def AArch64st3lanepost : SDNode<"AArch64ISD::ST3LANEpost", SDTypeProfile<1, 6, []>, [
1112+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1113+
def AArch64st4lanepost : SDNode<"AArch64ISD::ST4LANEpost", SDTypeProfile<1, 7, []>, [
1114+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1115+
1116+
// Scatter store
1117+
def AArch64sstnt1_index_pred: SDNode<"AArch64ISD::SSTNT1_INDEX_PRED", SDTypeProfile<0, 5, []>, [
1118+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1119+
// Non-temporal scatter store
1120+
def AArch64sst1q_index_pred: SDNode<"AArch64ISD::SST1Q_INDEX_PRED", SDTypeProfile<0, 5, []>, [
1121+
SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1122+
// Non-temporal gather loads
1123+
def AArch64gldnt1_index_merge_zero: SDNode<"AArch64ISD::GLDNT1_INDEX_MERGE_ZERO", SDTypeProfile<1, 4, []>, [
1124+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1125+
// Unsigned gather loads.
1126+
def AArch64gld1q_index_merge_zero: SDNode<"AArch64ISD::GLD1Q_INDEX_MERGE_ZERO", SDTypeProfile<1, 4, []>, [
1127+
SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1128+
10561129
// Match add node and also treat an 'or' node is as an 'add' if the or'ed operands
10571130
// have no common bits.
10581131
def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
@@ -5701,14 +5774,14 @@ def : Pat<(v2i64 (bswap (v2i64 V128:$Rn))),
57015774
(v2i64 (REV64v16i8 (v2i64 V128:$Rn)))>;
57025775

57035776
// Patterns for funnel shifts to be matched to equivalent REV instructions
5704-
def : Pat<(v2i64 (or (v2i64 (AArch64vshl (v2i64 V128:$Rn), (i32 32))),
5705-
(v2i64 (AArch64vlshr (v2i64 V128:$Rn), (i32 32))))),
5777+
def : Pat<(v2i64 (or (v2i64 (AArch64vshl (v2i64 V128:$Rn), (i32 32))),
5778+
(v2i64 (AArch64vlshr (v2i64 V128:$Rn), (i32 32))))),
57065779
(v2i64 (REV64v4i32 (v2i64 V128:$Rn)))>;
5707-
def : Pat<(v4i32 (or (v4i32 (AArch64vshl (v4i32 V128:$Rn), (i32 16))),
5708-
(v4i32 (AArch64vlshr (v4i32 V128:$Rn), (i32 16))))),
5780+
def : Pat<(v4i32 (or (v4i32 (AArch64vshl (v4i32 V128:$Rn), (i32 16))),
5781+
(v4i32 (AArch64vlshr (v4i32 V128:$Rn), (i32 16))))),
57095782
(v4i32 (REV32v8i16 (v4i32 V128:$Rn)))>;
5710-
def : Pat<(v2i32 (or (v2i32 (AArch64vshl (v2i32 V64:$Rn), (i32 16))),
5711-
(v2i32 (AArch64vlshr (v2i32 V64:$Rn), (i32 16))))),
5783+
def : Pat<(v2i32 (or (v2i32 (AArch64vshl (v2i32 V64:$Rn), (i32 16))),
5784+
(v2i32 (AArch64vlshr (v2i32 V64:$Rn), (i32 16))))),
57125785
(v2i32 (REV32v4i16 (v2i32 V64:$Rn)))>;
57135786

57145787
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp‎

Lines changed: 0 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -30,61 +30,6 @@ static cl::opt<bool>
3030
AArch64SelectionDAGInfo::AArch64SelectionDAGInfo()
3131
: SelectionDAGGenTargetInfo(AArch64GenSDNodeInfo) {}
3232

33-
const char *AArch64SelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
34-
#define MAKE_CASE(V) \
35-
case V: \
36-
return #V;
37-
38-
// These nodes don't have corresponding entries in *.td files yet.
39-
switch (static_cast<AArch64ISD::NodeType>(Opcode)) {
40-
MAKE_CASE(AArch64ISD::LD2post)
41-
MAKE_CASE(AArch64ISD::LD3post)
42-
MAKE_CASE(AArch64ISD::LD4post)
43-
MAKE_CASE(AArch64ISD::ST2post)
44-
MAKE_CASE(AArch64ISD::ST3post)
45-
MAKE_CASE(AArch64ISD::ST4post)
46-
MAKE_CASE(AArch64ISD::LD1x2post)
47-
MAKE_CASE(AArch64ISD::LD1x3post)
48-
MAKE_CASE(AArch64ISD::LD1x4post)
49-
MAKE_CASE(AArch64ISD::ST1x2post)
50-
MAKE_CASE(AArch64ISD::ST1x3post)
51-
MAKE_CASE(AArch64ISD::ST1x4post)
52-
MAKE_CASE(AArch64ISD::LD1DUPpost)
53-
MAKE_CASE(AArch64ISD::LD2DUPpost)
54-
MAKE_CASE(AArch64ISD::LD3DUPpost)
55-
MAKE_CASE(AArch64ISD::LD4DUPpost)
56-
MAKE_CASE(AArch64ISD::LD1LANEpost)
57-
MAKE_CASE(AArch64ISD::LD2LANEpost)
58-
MAKE_CASE(AArch64ISD::LD3LANEpost)
59-
MAKE_CASE(AArch64ISD::LD4LANEpost)
60-
MAKE_CASE(AArch64ISD::ST2LANEpost)
61-
MAKE_CASE(AArch64ISD::ST3LANEpost)
62-
MAKE_CASE(AArch64ISD::ST4LANEpost)
63-
MAKE_CASE(AArch64ISD::SVE_LD2_MERGE_ZERO)
64-
MAKE_CASE(AArch64ISD::SVE_LD3_MERGE_ZERO)
65-
MAKE_CASE(AArch64ISD::SVE_LD4_MERGE_ZERO)
66-
MAKE_CASE(AArch64ISD::GLD1Q_INDEX_MERGE_ZERO)
67-
MAKE_CASE(AArch64ISD::GLDNT1_INDEX_MERGE_ZERO)
68-
MAKE_CASE(AArch64ISD::SST1Q_INDEX_PRED)
69-
MAKE_CASE(AArch64ISD::SSTNT1_INDEX_PRED)
70-
MAKE_CASE(AArch64ISD::INDEX_VECTOR)
71-
MAKE_CASE(AArch64ISD::MRRS)
72-
MAKE_CASE(AArch64ISD::MSRR)
73-
}
74-
#undef MAKE_CASE
75-
76-
return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
77-
}
78-
79-
bool AArch64SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
80-
// These nodes don't have corresponding entries in *.td files yet.
81-
if (Opcode >= AArch64ISD::FIRST_MEMORY_OPCODE &&
82-
Opcode <= AArch64ISD::LAST_MEMORY_OPCODE)
83-
return true;
84-
85-
return SelectionDAGGenTargetInfo::isTargetMemoryOpcode(Opcode);
86-
}
87-
8833
void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
8934
const SDNode *N) const {
9035
#ifndef NDEBUG

‎llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h‎

Lines changed: 1 addition & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -20,92 +20,11 @@
2020
#include "AArch64GenSDNodeInfo.inc"
2121

2222
namespace llvm {
23-
namespace AArch64ISD {
24-
25-
// For predicated nodes where the result is a vector, the operation is
26-
// controlled by a governing predicate and the inactive lanes are explicitly
27-
// defined with a value, please stick the following naming convention:
28-
//
29-
// _MERGE_OP<n> The result value is a vector with inactive lanes equal
30-
// to source operand OP<n>.
31-
//
32-
// _MERGE_ZERO The result value is a vector with inactive lanes
33-
// actively zeroed.
34-
//
35-
// _MERGE_PASSTHRU The result value is a vector with inactive lanes equal
36-
// to the last source operand which only purpose is being
37-
// a passthru value.
38-
//
39-
// For other cases where no explicit action is needed to set the inactive lanes,
40-
// or when the result is not a vector and it is needed or helpful to
41-
// distinguish a node from similar unpredicated nodes, use:
42-
//
43-
// _PRED
44-
//
45-
enum NodeType : unsigned {
46-
INDEX_VECTOR = GENERATED_OPCODE_END,
47-
48-
// Structured loads.
49-
SVE_LD2_MERGE_ZERO,
50-
SVE_LD3_MERGE_ZERO,
51-
SVE_LD4_MERGE_ZERO,
52-
53-
// Unsigned gather loads.
54-
GLD1Q_INDEX_MERGE_ZERO,
55-
56-
// Non-temporal gather loads
57-
GLDNT1_INDEX_MERGE_ZERO,
58-
59-
// Scatter store
60-
SST1Q_INDEX_PRED,
61-
62-
// Non-temporal scatter store
63-
SSTNT1_INDEX_PRED,
64-
65-
// 128-bit system register accesses
66-
// lo64, hi64, chain = MRRS(chain, sysregname)
67-
MRRS,
68-
// chain = MSRR(chain, sysregname, lo64, hi64)
69-
MSRR,
70-
71-
// NEON Load/Store with post-increment base updates
72-
FIRST_MEMORY_OPCODE,
73-
LD2post = FIRST_MEMORY_OPCODE,
74-
LD3post,
75-
LD4post,
76-
ST2post,
77-
ST3post,
78-
ST4post,
79-
LD1x2post,
80-
LD1x3post,
81-
LD1x4post,
82-
ST1x2post,
83-
ST1x3post,
84-
ST1x4post,
85-
LD1DUPpost,
86-
LD2DUPpost,
87-
LD3DUPpost,
88-
LD4DUPpost,
89-
LD1LANEpost,
90-
LD2LANEpost,
91-
LD3LANEpost,
92-
LD4LANEpost,
93-
ST2LANEpost,
94-
ST3LANEpost,
95-
ST4LANEpost,
96-
LAST_MEMORY_OPCODE = ST4LANEpost,
97-
};
98-
99-
} // namespace AArch64ISD
10023

10124
class AArch64SelectionDAGInfo : public SelectionDAGGenTargetInfo {
10225
public:
10326
AArch64SelectionDAGInfo();
10427

105-
const char *getTargetNodeName(unsigned Opcode) const override;
106-
107-
bool isTargetMemoryOpcode(unsigned Opcode) const override;
108-
10928
void verifyTargetNode(const SelectionDAG &DAG,
11029
const SDNode *N) const override;
11130

@@ -143,6 +62,6 @@ class AArch64SelectionDAGInfo : public SelectionDAGGenTargetInfo {
14362
SDValue Src, SDValue Size,
14463
RTLIB::Libcall LC) const;
14564
};
146-
}
65+
} // namespace llvm
14766

14867
#endif

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