Use fpext and fptrunc instead

Author: tclin914

clang/lib/CodeGen/TargetBuiltins/RISCV.cpp

@@ -415,11 +415,9 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
 
   // XAndesBFHCvt
   case RISCV::BI__builtin_riscv_nds_fcvt_s_bf16:
-    ID = Intrinsic::riscv_nds_fcvt_s_bf16;
-    break;
+    return Builder.CreateFPExt(Ops[0], FloatTy);
   case RISCV::BI__builtin_riscv_nds_fcvt_bf16_s:
-    ID = Intrinsic::riscv_nds_fcvt_bf16_s;
-    break;
+    return Builder.CreateFPTrunc(Ops[0], BFloatTy);
 
     // Vector builtins are handled from here.
 #include "clang/Basic/riscv_vector_builtin_cg.inc"

clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c

@@ -8,7 +8,7 @@
 
 // CHECK-LABEL: @test_fcvt_s_bf16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call float @llvm.riscv.nds.fcvt.s.bf16(bfloat [[BF:%.*]])
+// CHECK-NEXT:    [[TMP0:%.*]] = fpext bfloat [[BF:%.*]] to float
 // CHECK-NEXT:    ret float [[TMP0]]
 //
 float test_fcvt_s_bf16(__bf16 bf) {
@@ -17,7 +17,7 @@ float test_fcvt_s_bf16(__bf16 bf) {
 
 // CHECK-LABEL: @test_fcvt_bf16_s(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call bfloat @llvm.riscv.nds.fcvt.bf16.s(float [[SF:%.*]])
+// CHECK-NEXT:    [[TMP0:%.*]] = fptrunc float [[SF:%.*]] to bfloat
 // CHECK-NEXT:    ret bfloat [[TMP0]]
 //
 __bf16 test_fcvt_bf16_s(float sf) {

clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c

@@ -6,7 +6,7 @@
 
 // CHECK-LABEL: @test_fcvt_s_bf16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call float @llvm.riscv.nds.fcvt.s.bf16(bfloat [[BF:%.*]])
+// CHECK-NEXT:    [[TMP0:%.*]] = fpext bfloat [[BF:%.*]] to float
 // CHECK-NEXT:    ret float [[TMP0]]
 //
 float test_fcvt_s_bf16(__bf16 bf) {
@@ -15,7 +15,7 @@ float test_fcvt_s_bf16(__bf16 bf) {
 
 // CHECK-LABEL: @test_fcvt_bf16_s(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call bfloat @llvm.riscv.nds.fcvt.bf16.s(float [[SF:%.*]])
+// CHECK-NEXT:    [[TMP0:%.*]] = fptrunc float [[SF:%.*]] to bfloat
 // CHECK-NEXT:    ret bfloat [[TMP0]]
 //
 __bf16 test_fcvt_bf16_s(float sf) {

llvm/include/llvm/IR/IntrinsicsRISCVXAndes.td

@@ -11,15 +11,6 @@
 //===----------------------------------------------------------------------===//
 
 let TargetPrefix = "riscv" in {
-  // Andes Scalar BFloat16 Conversion Extension
-  def int_riscv_nds_fcvt_s_bf16
-      : DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_bfloat_ty],
-                              [IntrNoMem, IntrSpeculatable]>;
-
-  def int_riscv_nds_fcvt_bf16_s
-      : DefaultAttrsIntrinsic<[llvm_bfloat_ty], [llvm_float_ty],
-                              [IntrNoMem, IntrSpeculatable]>;
-
   // Andes Vector BFloat16 Conversion Extension
   def int_riscv_nds_vfwcvt_s_bf16 : RISCVConversionUnMasked;
   def int_riscv_nds_vfncvt_bf16_s : RISCVConversionUnMaskedRoundingMode;

llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

@@ -768,9 +768,9 @@ def : Sh3AddPat<NDS_LEA_D_ZE>;
 } // Predicates = [HasVendorXAndesPerf, IsRV64]
 
 let Predicates = [HasVendorXAndesBFHCvt] in {
-def : Pat<(int_riscv_nds_fcvt_s_bf16 (bf16 FPR16:$rs)),
+def : Pat<(fpextend (bf16 FPR16:$rs)),
           (NDS_FCVT_S_BF16 (bf16 FPR16:$rs))>;
-def : Pat<(bf16 (int_riscv_nds_fcvt_bf16_s FPR32:$rs)),
+def : Pat<(bf16 (fpround FPR32:$rs)),
           (NDS_FCVT_BF16_S FPR32:$rs)>;
 } // Predicates = [HasVendorXAndesBFHCvt]
 

llvm/test/CodeGen/RISCV/xandesbfhcvt.ll

@@ -11,7 +11,7 @@ define float @fcvt_s_bf16(bfloat %a) nounwind {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    nds.fcvt.s.bf16 fa0, fa0
 ; CHECK-NEXT:    ret
-  %1 = call float @llvm.riscv.nds.fcvt.s.bf16(bfloat %a)
+  %1 = fpext bfloat %a to float
   ret float %1
 }
 
@@ -22,6 +22,6 @@ define bfloat @fcvt_bf16_s(float %a) nounwind {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    nds.fcvt.bf16.s fa0, fa0
 ; CHECK-NEXT:    ret
-  %1 = call bfloat @llvm.riscv.nds.fcvt.bf16.s(float %a)
+  %1 = fptrunc float %a to bfloat
   ret bfloat %1
 }