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[RISCV] Relax destination instruction dag operand matching in CompressInstEmitter
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3 files changed

+61
-7
lines changed

3 files changed

+61
-7
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1638,6 +1638,24 @@ def : CompressPat<(QC_E_ADDAI X2, simm10_lsb0000nonzero:$imm),
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(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
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def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm),
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(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
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def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
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(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
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def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
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(ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
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def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
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(ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
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def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
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(XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
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def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12:$imm),
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(ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
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def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12:$imm),
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(ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
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def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12:$imm),
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(ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
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def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12:$imm),
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(XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
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} // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]
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let Predicates = [HasVendorXqciac, IsRV32] in {

llvm/test/MC/RISCV/xqcilia-valid.s

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,3 +123,43 @@ qc.e.addai x2, 48
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# CHECK-NOALIAS: c.andi s1, -1
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# CHECK-ENC: encoding: [0xfd,0x98]
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qc.e.andai x9, 4294967295
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# CHECK-ALIAS: addi t0, t2, 400
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# CHECK-NOALIAS: addi t0, t2, 400
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# CHECK-ENC: encoding: [0x93,0x82,0x03,0x19]
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qc.e.addi x5, x7, 400
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# CHECK-ALIAS: andi t0, t2, 750
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# CHECK-NOALIAS: andi t0, t2, 750
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# CHECK-ENC: encoding: [0x93,0xf2,0xe3,0x2e]
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qc.e.andi x5, x7, 750
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# CHECK-ALIAS: ori t0, t2, 854
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# CHECK-NOALIAS: ori t0, t2, 854
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# CHECK-ENC: encoding: [0x93,0xe2,0x63,0x35]
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qc.e.ori x5, x7, 854
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# CHECK-ALIAS: xori t0, t2, -200
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# CHECK-NOALIAS: xori t0, t2, -200
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# CHECK-ENC: encoding: [0x93,0xc2,0x83,0xf3]
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qc.e.xori x5, x7, -200
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# CHECK-ALIAS: addi t2, t2, 400
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# CHECK-NOALIAS: addi t2, t2, 400
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# CHECK-ENC: encoding: [0x93,0x83,0x03,0x19]
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qc.e.addai x7, 400
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# CHECK-ALIAS: andi t2, t2, 750
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# CHECK-NOALIAS: andi t2, t2, 750
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# CHECK-ENC: encoding: [0x93,0xf3,0xe3,0x2e]
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qc.e.andai x7, 750
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# CHECK-ALIAS: ori t2, t2, 854
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# CHECK-NOALIAS: ori t2, t2, 854
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# CHECK-ENC: encoding: [0x93,0xe3,0x63,0x35]
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qc.e.orai x7, 854
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# CHECK-ALIAS: xori t2, t2, -200
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# CHECK-NOALIAS: xori t2, t2, -200
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# CHECK-ENC: encoding: [0x93,0xc3,0x83,0xf3]
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qc.e.xorai x7, -200

llvm/utils/TableGen/CompressInstEmitter.cpp

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -171,10 +171,6 @@ bool CompressInstEmitter::validateTypes(const Record *DagOpType,
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bool IsSourceInst) {
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if (DagOpType == InstOpType)
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return true;
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// Only source instruction operands are allowed to not match Input Dag
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// operands.
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if (!IsSourceInst)
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return false;
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if (DagOpType->isSubClassOf("RegisterClass") &&
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InstOpType->isSubClassOf("RegisterClass")) {
@@ -258,9 +254,9 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
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continue;
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}
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// Validate that Dag operand type matches the type defined in the
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// corresponding instruction. Operands in the input Dag pattern are
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// allowed to be a subclass of the type specified in corresponding
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// instruction operand instead of being an exact match.
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// corresponding instruction. Operands in the input and output Dag
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// patterns are allowed to be a subclass of the type specified in the
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// corresponding instruction operand instead of being an exact match.
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if (!validateTypes(DI->getDef(), OpndRec, IsSourceInst))
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PrintFatalError(Rec->getLoc(),
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"Error in Dag '" + Dag->getAsString() +

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