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1 parent b88f7f6 commit 7a7ecafCopy full SHA for 7a7ecaf
mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
@@ -1741,7 +1741,8 @@ LogicalResult ScaledExtPacked816OpLowering::matchAndRewrite(
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"no intrinsic matching packed scaled conversion on the given chipset");
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OperationState loweredOp(loc, *maybeIntrinsic);
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- loweredOp.addTypes({op.getResult().getType()});
+ Type llvmResultType = typeConverter->convertType(op.getResult().getType());
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+ loweredOp.addTypes({llvmResultType});
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loweredOp.addOperands({castedSource, castedScale});
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SmallVector<NamedAttribute, 1> attrs;
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