[M68k]: always use the movem instruction for register spills

In the previous implementation, the mov instruction was used for 8-bit
register spills. However, this instruction has the side effect of
overwriting the CCR. When a spill is inserted between a compare and a
branch instruction, this would cause the necessary condition flags to be
overwritten. As 8-bit spills are already assigned 16-bit stack slots,
the 16-bit movem instruction, which doesn't affect the CCR, may be used
instead.

Fixes #106209.

Author: TechnoElf

llvm/lib/Target/M68k/M68kInstrInfo.cpp

@@ -791,22 +791,25 @@ namespace {
 unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC,
                                const TargetRegisterInfo *TRI,
                                const M68kSubtarget &STI, bool load) {
-  switch (TRI->getRegSizeInBits(*RC)) {
+  switch (TRI->getSpillSize(*RC)) {
   default:
+    LLVM_DEBUG(
+        dbgs() << "Cannot determine appropriate opcode for load/store to/from "
+               << TRI->getName(Reg) << " of class " << TRI->getRegClassName(RC)
+               << " with spill size " << TRI->getSpillSize(*RC) << '\n');
     llvm_unreachable("Unknown spill size");
-  case 8:
+  case 2:
+    if (M68k::XR16RegClass.hasSubClassEq(RC))
+      return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
     if (M68k::DR8RegClass.hasSubClassEq(RC))
-      return load ? M68k::MOV8dp : M68k::MOV8pd;
+      return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
     if (M68k::CCRCRegClass.hasSubClassEq(RC))
-      return load ? M68k::MOV16cp : M68k::MOV16pc;
-
-    llvm_unreachable("Unknown 1-byte regclass");
-  case 16:
-    assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
-    return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
-  case 32:
-    assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass");
-    return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;
+      return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
+    llvm_unreachable("Unknown 2-byte regclass");
+  case 4:
+    if (M68k::XR32RegClass.hasSubClassEq(RC))
+      return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;
+    llvm_unreachable("Unknown 4-byte regclass");
   }
 }
 

llvm/test/CodeGen/M68k/PR57660.ll

@@ -8,10 +8,10 @@ define dso_local void @foo1() {
 ; CHECK-NEXT:    suba.l #2, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_offset -6
 ; CHECK-NEXT:    moveq #0, %d0
-; CHECK-NEXT:    move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:    movem.w %d0, (0,%sp)
 ; CHECK-NEXT:  .LBB0_1: ; %do.body
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT:    movem.w (0,%sp), %d0
 ; CHECK-NEXT:    cmpi.b #0, %d0
 ; CHECK-NEXT:    bne .LBB0_1
 ; CHECK-NEXT:  ; %bb.2: ; %do.end
@@ -39,24 +39,24 @@ define i32 @foo2(ptr noundef %0) {
 ; CHECK-NEXT:    .cfi_def_cfa_offset -8
 ; CHECK-NEXT:    move.l (8,%sp), %a0
 ; CHECK-NEXT:    move.b (%a0), %d0
-; CHECK-NEXT:    move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:    movem.w %d0, (0,%sp)
 ; CHECK-NEXT:    and.b #1, %d0
-; CHECK-NEXT:    move.b %d0, (2,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:    movem.w %d0, (2,%sp)
 ; CHECK-NEXT:    sub.b #1, %d0
 ; CHECK-NEXT:    bgt .LBB1_2
 ; CHECK-NEXT:  ; %bb.1: ; %if
-; CHECK-NEXT:    move.b (2,%sp), %d0 ; 1-byte Folded Reload
-; CHECK-NEXT:    move.b (0,%sp), %d1 ; 1-byte Folded Reload
+; CHECK-NEXT:    movem.w (2,%sp), %d0
+; CHECK-NEXT:    movem.w (0,%sp), %d1
 ; CHECK-NEXT:    add.b %d1, %d0
 ; CHECK-NEXT:    bra .LBB1_3
 ; CHECK-NEXT:  .LBB1_2: ; %else
-; CHECK-NEXT:    move.b (2,%sp), %d1 ; 1-byte Folded Reload
-; CHECK-NEXT:    move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT:    movem.w (2,%sp), %d1
+; CHECK-NEXT:    movem.w (0,%sp), %d0
 ; CHECK-NEXT:    sub.b %d1, %d0
-; CHECK-NEXT:    move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT:    movem.w %d0, (0,%sp)
 ; CHECK-NEXT:  .LBB1_3: ; %cont
-; CHECK-NEXT:    move.b %d0, (2,%sp) ; 1-byte Folded Spill
-; CHECK-NEXT:    move.b (2,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT:    movem.w %d0, (2,%sp)
+; CHECK-NEXT:    movem.w (2,%sp), %d0
 ; CHECK-NEXT:    ext.w %d0
 ; CHECK-NEXT:    ext.l %d0
 ; CHECK-NEXT:    adda.l #4, %sp