StringLiteral

optimisan · optimisan · commit 7af9e5eb6fb6 · 2024-10-09T05:52:59.000Z
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1218,7 +1218,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return {};
   }
 
-  virtual SmallVector<SmallString<8>>
+  virtual SmallVector<StringLiteral>
   getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {
     return {};
   }
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -323,7 +323,7 @@ static void printRegFlags(Register Reg,
                           const TargetRegisterInfo *TRI) {
   auto FlagValues = TRI->getVRegFlagsOfReg(Reg, MF);
   for (auto &Flag : FlagValues) {
-    RegisterFlags.push_back(yaml::FlowStringValue(Flag.str().str()));
+    RegisterFlags.push_back(yaml::FlowStringValue(Flag.str()));
   }
 }
 

Original file line number	Diff line number	Diff line change
`@@ -1218,7 +1218,7 @@ class TargetRegisterInfo : public MCRegisterInfo {`
`1218`	`1218`	`return {};`
`1219`	`1219`	`}`
`1220`	`1220`
`1221`		`- virtual SmallVector<SmallString<8>>`
	`1221`	`+ virtual SmallVector<StringLiteral>`
`1222`	`1222`	`getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {`
`1223`	`1223`	`return {};`
`1224`	`1224`	`}`
Original file line number	Diff line number	Diff line change
`@@ -323,7 +323,7 @@ static void printRegFlags(Register Reg,`
`323`	`323`	`const TargetRegisterInfo *TRI) {`
`324`	`324`	`auto FlagValues = TRI->getVRegFlagsOfReg(Reg, MF);`
`325`	`325`	`for (auto &Flag : FlagValues) {`
`326`		`- RegisterFlags.push_back(yaml::FlowStringValue(Flag.str().str()));`
	`326`	`+ RegisterFlags.push_back(yaml::FlowStringValue(Flag.str()));`
`327`	`327`	`}`
`328`	`328`	`}`
`329`	`329`