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gisel update
1 parent a955426 commit 7b0ce27

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+21
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llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -639,7 +639,7 @@ bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
639639
LLT SrcTy = MRI->getType(MI.getOperand(1).getReg());
640640

641641
const unsigned SrcSize = SrcTy.getSizeInBits();
642-
if (SrcSize < 32)
642+
if (SrcSize < 16)
643643
return selectImpl(MI, *CoverageInfo);
644644

645645
const DebugLoc &DL = MI.getDebugLoc();
@@ -1478,10 +1478,17 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const {
14781478
if (Opcode == -1)
14791479
return false;
14801480

1481-
MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
1482-
I.getOperand(0).getReg())
1483-
.add(I.getOperand(2))
1484-
.add(I.getOperand(3));
1481+
MachineInstrBuilder ICmp =
1482+
BuildMI(*BB, &I, DL, TII.get(Opcode), I.getOperand(0).getReg());
1483+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers))
1484+
ICmp.addImm(0);
1485+
ICmp.add(I.getOperand(2));
1486+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1_modifiers))
1487+
ICmp.addImm(0);
1488+
ICmp.add(I.getOperand(3));
1489+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel))
1490+
ICmp.addImm(0); // op_sel
1491+
14851492
RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
14861493
*TRI.getBoolRC(), *MRI);
14871494
bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
@@ -4597,6 +4604,7 @@ AMDGPUInstructionSelector::selectVOP3OpSelMods(MachineOperand &Root) const {
45974604
}};
45984605
}
45994606

4607+
// FIXME-TRUE16 remove when fake16 is removed
46004608
InstructionSelector::ComplexRendererFns
46014609
AMDGPUInstructionSelector::selectVINTERPMods(MachineOperand &Root) const {
46024610
Register Src;
@@ -5841,6 +5849,14 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
58415849
CheckAbsNeg();
58425850
}
58435851

5852+
// Since we looked through FPEXT and removed it, we must also remove
5853+
// G_TRUNC. G_TRUNC to 16-bits would have a destination in RC VGPR_16, which
5854+
// is not compatible with MadMix instructions
5855+
Register PeekSrc = Src;
5856+
if (Subtarget->useRealTrue16Insts() &&
5857+
mi_match(PeekSrc, *MRI, m_GTrunc(m_Reg(PeekSrc))))
5858+
Src = PeekSrc;
5859+
58445860
Matched = true;
58455861
}
58465862

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