Skip to content

Commit 7b6a66d

Browse files
shiltianshiltian
committed
[IR] Introduce T<address space> to DataLayout to represent flat address space if a target supports it
1 parent b334ca6 commit 7b6a66d

File tree

15 files changed

+83
-37
lines changed

15 files changed

+83
-37
lines changed

‎clang/lib/Basic/Targets/AMDGPU.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ static const char *const DataLayoutStringAMDGCN =
3636
"-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:"
3737
"32-v48:64-v96:128"
3838
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
39-
"-ni:7:8:9";
39+
"-ni:7:8:9-T0";
4040

4141
const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
4242
llvm::AMDGPUAS::FLAT_ADDRESS, // Default

‎clang/lib/Basic/Targets/NVPTX.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -66,12 +66,12 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
6666
HasFloat16 = true;
6767

6868
if (TargetPointerWidth == 32)
69-
resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
69+
resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64-T0");
7070
else if (Opts.NVPTXUseShortPointers)
71-
resetDataLayout(
72-
"e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
71+
resetDataLayout("e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:"
72+
"32-n16:32:64-T0");
7373
else
74-
resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
74+
resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64-T0");
7575

7676
// If possible, get a TargetInfo for our host triple, so we can match its
7777
// types.

‎clang/test/CodeGen/target-data.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -160,11 +160,11 @@
160160

161161
// RUN: %clang_cc1 -triple nvptx-unknown -o - -emit-llvm %s | \
162162
// RUN: FileCheck %s -check-prefix=NVPTX
163-
// NVPTX: target datalayout = "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
163+
// NVPTX: target datalayout = "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64-T0"
164164

165165
// RUN: %clang_cc1 -triple nvptx64-unknown -o - -emit-llvm %s | \
166166
// RUN: FileCheck %s -check-prefix=NVPTX64
167-
// NVPTX64: target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
167+
// NVPTX64: target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64-T0"
168168

169169
// RUN: %clang_cc1 -triple r600-unknown -o - -emit-llvm %s | \
170170
// RUN: FileCheck %s -check-prefix=R600
@@ -176,12 +176,12 @@
176176

177177
// RUN: %clang_cc1 -triple amdgcn-unknown -target-cpu hawaii -o - -emit-llvm %s \
178178
// RUN: | FileCheck %s -check-prefix=R600SI
179-
// R600SI: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
179+
// R600SI: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-T0"
180180

181181
// Test default -target-cpu
182182
// RUN: %clang_cc1 -triple amdgcn-unknown -o - -emit-llvm %s \
183183
// RUN: | FileCheck %s -check-prefix=R600SIDefault
184-
// R600SIDefault: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
184+
// R600SIDefault: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-T0"
185185

186186
// RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \
187187
// RUN: FileCheck %s -check-prefix=AARCH64

‎clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %clang_cc1 %s -O0 -triple amdgcn -emit-llvm -o - | FileCheck %s
22
// RUN: %clang_cc1 %s -O0 -triple amdgcn---opencl -emit-llvm -o - | FileCheck %s
33

4-
// CHECK: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
4+
// CHECK: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-T0"
55
void foo(void) {}

‎lld/test/ELF/lto/amdgcn-oses.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
2525

2626
;--- amdhsa.ll
2727
target triple = "amdgcn-amd-amdhsa"
28-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
28+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-T0"
2929

3030
!llvm.module.flags = !{!0}
3131
!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
@@ -36,15 +36,15 @@ define void @_start() {
3636

3737
;--- amdpal.ll
3838
target triple = "amdgcn-amd-amdpal"
39-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
39+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-T0"
4040

4141
define amdgpu_cs void @_start() {
4242
ret void
4343
}
4444

4545
;--- mesa3d.ll
4646
target triple = "amdgcn-amd-mesa3d"
47-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
47+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-T0"
4848

4949
define void @_start() {
5050
ret void

‎lld/test/ELF/lto/amdgcn.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
; Make sure the amdgcn triple is handled
66

77
target triple = "amdgcn-amd-amdhsa"
8-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
8+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-T0"
99

1010
define void @_start() {
1111
ret void

‎llvm/docs/LangRef.rst‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3050,6 +3050,25 @@ as follows:
30503050
address space 0, this property only affects the default value to be used
30513051
when creating globals without additional contextual information (e.g. in
30523052
LLVM passes).
3053+
``T<address space>``
3054+
Specifies the 'flat' address space for a target. Some targets may have an
3055+
address space that allows access to multiple memory segments, each with
3056+
distinct address spaces. Accessing memory through a pointer in this address
3057+
space is valid but may be slower than using a pointer with a more specific
3058+
address space. When a pointer is converted to this address space,
3059+
optimizations can attempt to replace the access with one using the original
3060+
address space. This is the 'flat' address space. It is intended for targets
3061+
with varying pointer representations, which can be converted using the
3062+
addrspacecast instruction. It is important to note that the flat address
3063+
space is not always equivalent to address space 0, which LLVM commonly
3064+
refers to as the generic address space. For instance, in SPIR and SPIR-V,
3065+
address space 4 is designated as the flat address space. Additionally, the
3066+
flat address space must correspond to an existing address space of the
3067+
target. Specifying an address space as 'flat' address space does not change
3068+
any inherent characteristics of the original address spaces, nor does it
3069+
guarantee any additional properties. If this specification is absent, it
3070+
indicates that the target does not support a flat address space for
3071+
optimization.
30533072

30543073
.. _alloca_addrspace:
30553074

‎llvm/docs/ReleaseNotes.rst‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,9 @@ Changes to the LLVM IR
5656

5757
* Added ``usub_cond`` and ``usub_sat`` operations to ``atomicrmw``.
5858

59+
* Added ``T<address space>`` to data layout to represent flat address space if a
60+
target has it.
61+
5962
Changes to LLVM infrastructure
6063
------------------------------
6164

‎llvm/include/llvm/IR/DataLayout.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,12 +88,16 @@ class DataLayout {
8888
/// The function pointer alignment is a multiple of the function alignment.
8989
MultipleOfFunctionAlign,
9090
};
91+
92+
enum { AS_INVALID = ~0U };
93+
9194
private:
9295
bool BigEndian = false;
9396

9497
unsigned AllocaAddrSpace = 0;
9598
unsigned ProgramAddrSpace = 0;
9699
unsigned DefaultGlobalsAddrSpace = 0;
100+
unsigned FlatAddressSpace = AS_INVALID;
97101

98102
MaybeAlign StackNaturalAlign;
99103
MaybeAlign FunctionPtrAlign;
@@ -245,6 +249,7 @@ class DataLayout {
245249
unsigned getDefaultGlobalsAddressSpace() const {
246250
return DefaultGlobalsAddrSpace;
247251
}
252+
unsigned getFlatAddressSpace() const { return FlatAddressSpace; }
248253

249254
bool hasMicrosoftFastStdCallMangling() const {
250255
return ManglingMode == MM_WinCOFFX86;

‎llvm/lib/IR/AutoUpgrade.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5451,6 +5451,10 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
54515451
if (!DL.contains("-p9") && !DL.starts_with("p9"))
54525452
Res.append("-p9:192:256:256:32");
54535453

5454+
// Add flat address space.
5455+
if (!DL.contains("-T0") && !DL.starts_with("T0"))
5456+
Res.append("-T0");
5457+
54545458
return Res;
54555459
}
54565460

@@ -5501,6 +5505,12 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
55015505
Res = (Ref.take_front(I) + "-f80:128-" + Ref.drop_front(I + 8)).str();
55025506
}
55035507

5508+
if (T.isNVPTX()) {
5509+
// Add flat address space.
5510+
if (!DL.contains("-T0") && !DL.starts_with("T0"))
5511+
Res.append("-T0");
5512+
}
5513+
55045514
return Res;
55055515
}
55065516

0 commit comments

Comments
 (0)