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[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
1 parent 3c9db3a commit 7ba4968

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8 files changed

+213
-141
lines changed

8 files changed

+213
-141
lines changed

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,11 @@ def FeatureStdExtZfinx
348348
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
349349
AssemblerPredicate<(all_of FeatureStdExtZfinx),
350350
"'Zfinx' (Float in Integer)">;
351+
def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,
352+
AssemblerPredicate<(any_of FeatureStdExtF,
353+
FeatureStdExtZfinx),
354+
"'F' (Single-Precision Floating-Point) or "
355+
"'Zfinx' (Float in Integer)">;
351356

352357
def FeatureStdExtZdinx
353358
: RISCVExtension<"zdinx", 1, 0,

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td‎

Lines changed: 19 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -400,23 +400,10 @@ def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
400400
// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
401401
//===----------------------------------------------------------------------===//
402402

403-
let Predicates = [HasStdExtF] in {
404-
def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
405-
def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
406-
407-
def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
408-
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
409-
def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
410-
411-
// fgt.s/fge.s are recognised by the GNU assembler but the canonical
412-
// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
413-
def : InstAlias<"fgt.s $rd, $rs, $rt",
414-
(FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
415-
def : InstAlias<"fge.s $rd, $rs, $rt",
416-
(FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
417-
403+
let Predicates = [HasStdExtFOrZfinx] in {
418404
// The following csr instructions actually alias instructions from the base ISA.
419-
// However, it only makes sense to support them when the F extension is enabled.
405+
// However, it only makes sense to support them when the F or Zfinx extension is
406+
// enabled.
420407
// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr".
421408
def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>;
422409
def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
@@ -439,6 +426,22 @@ def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GP
439426
def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>;
440427
def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>;
441428
def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>;
429+
} // Predicates = [HasStdExtFOrZfinx]
430+
431+
let Predicates = [HasStdExtF] in {
432+
def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
433+
def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
434+
435+
def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
436+
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
437+
def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
438+
439+
// fgt.s/fge.s are recognised by the GNU assembler but the canonical
440+
// flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
441+
def : InstAlias<"fgt.s $rd, $rs, $rt",
442+
(FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
443+
def : InstAlias<"fge.s $rd, $rs, $rt",
444+
(FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
442445

443446
// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
444447
// spellings should be supported by standard tools.

‎llvm/test/CodeGen/RISCV/double-fcmp-strict.ll‎

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -68,18 +68,18 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind strictfp {
6868
;
6969
; RV32IZFINXZDINX-LABEL: fcmp_ogt:
7070
; RV32IZFINXZDINX: # %bb.0:
71-
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
71+
; RV32IZFINXZDINX-NEXT: frflags a5
7272
; RV32IZFINXZDINX-NEXT: flt.d a4, a2, a0
73-
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
73+
; RV32IZFINXZDINX-NEXT: fsflags a5
7474
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
7575
; RV32IZFINXZDINX-NEXT: mv a0, a4
7676
; RV32IZFINXZDINX-NEXT: ret
7777
;
7878
; RV64IZFINXZDINX-LABEL: fcmp_ogt:
7979
; RV64IZFINXZDINX: # %bb.0:
80-
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
80+
; RV64IZFINXZDINX-NEXT: frflags a3
8181
; RV64IZFINXZDINX-NEXT: flt.d a2, a1, a0
82-
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
82+
; RV64IZFINXZDINX-NEXT: fsflags a3
8383
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
8484
; RV64IZFINXZDINX-NEXT: mv a0, a2
8585
; RV64IZFINXZDINX-NEXT: ret
@@ -119,18 +119,18 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp {
119119
;
120120
; RV32IZFINXZDINX-LABEL: fcmp_oge:
121121
; RV32IZFINXZDINX: # %bb.0:
122-
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
122+
; RV32IZFINXZDINX-NEXT: frflags a5
123123
; RV32IZFINXZDINX-NEXT: fle.d a4, a2, a0
124-
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
124+
; RV32IZFINXZDINX-NEXT: fsflags a5
125125
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
126126
; RV32IZFINXZDINX-NEXT: mv a0, a4
127127
; RV32IZFINXZDINX-NEXT: ret
128128
;
129129
; RV64IZFINXZDINX-LABEL: fcmp_oge:
130130
; RV64IZFINXZDINX: # %bb.0:
131-
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
131+
; RV64IZFINXZDINX-NEXT: frflags a3
132132
; RV64IZFINXZDINX-NEXT: fle.d a2, a1, a0
133-
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
133+
; RV64IZFINXZDINX-NEXT: fsflags a3
134134
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
135135
; RV64IZFINXZDINX-NEXT: mv a0, a2
136136
; RV64IZFINXZDINX-NEXT: ret
@@ -172,18 +172,18 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp {
172172
;
173173
; RV32IZFINXZDINX-LABEL: fcmp_olt:
174174
; RV32IZFINXZDINX: # %bb.0:
175-
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
175+
; RV32IZFINXZDINX-NEXT: frflags a5
176176
; RV32IZFINXZDINX-NEXT: flt.d a4, a0, a2
177-
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
177+
; RV32IZFINXZDINX-NEXT: fsflags a5
178178
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
179179
; RV32IZFINXZDINX-NEXT: mv a0, a4
180180
; RV32IZFINXZDINX-NEXT: ret
181181
;
182182
; RV64IZFINXZDINX-LABEL: fcmp_olt:
183183
; RV64IZFINXZDINX: # %bb.0:
184-
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
184+
; RV64IZFINXZDINX-NEXT: frflags a3
185185
; RV64IZFINXZDINX-NEXT: flt.d a2, a0, a1
186-
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
186+
; RV64IZFINXZDINX-NEXT: fsflags a3
187187
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
188188
; RV64IZFINXZDINX-NEXT: mv a0, a2
189189
; RV64IZFINXZDINX-NEXT: ret
@@ -223,18 +223,18 @@ define i32 @fcmp_ole(double %a, double %b) nounwind strictfp {
223223
;
224224
; RV32IZFINXZDINX-LABEL: fcmp_ole:
225225
; RV32IZFINXZDINX: # %bb.0:
226-
; RV32IZFINXZDINX-NEXT: csrr a5, fflags
226+
; RV32IZFINXZDINX-NEXT: frflags a5
227227
; RV32IZFINXZDINX-NEXT: fle.d a4, a0, a2
228-
; RV32IZFINXZDINX-NEXT: csrw fflags, a5
228+
; RV32IZFINXZDINX-NEXT: fsflags a5
229229
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
230230
; RV32IZFINXZDINX-NEXT: mv a0, a4
231231
; RV32IZFINXZDINX-NEXT: ret
232232
;
233233
; RV64IZFINXZDINX-LABEL: fcmp_ole:
234234
; RV64IZFINXZDINX: # %bb.0:
235-
; RV64IZFINXZDINX-NEXT: csrr a3, fflags
235+
; RV64IZFINXZDINX-NEXT: frflags a3
236236
; RV64IZFINXZDINX-NEXT: fle.d a2, a0, a1
237-
; RV64IZFINXZDINX-NEXT: csrw fflags, a3
237+
; RV64IZFINXZDINX-NEXT: fsflags a3
238238
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
239239
; RV64IZFINXZDINX-NEXT: mv a0, a2
240240
; RV64IZFINXZDINX-NEXT: ret
@@ -281,27 +281,27 @@ define i32 @fcmp_one(double %a, double %b) nounwind strictfp {
281281
;
282282
; RV32IZFINXZDINX-LABEL: fcmp_one:
283283
; RV32IZFINXZDINX: # %bb.0:
284-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
284+
; RV32IZFINXZDINX-NEXT: frflags a4
285285
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
286-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
286+
; RV32IZFINXZDINX-NEXT: fsflags a4
287287
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
288-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
288+
; RV32IZFINXZDINX-NEXT: frflags a4
289289
; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
290-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
290+
; RV32IZFINXZDINX-NEXT: fsflags a4
291291
; RV32IZFINXZDINX-NEXT: or a4, a6, a5
292292
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
293293
; RV32IZFINXZDINX-NEXT: mv a0, a4
294294
; RV32IZFINXZDINX-NEXT: ret
295295
;
296296
; RV64IZFINXZDINX-LABEL: fcmp_one:
297297
; RV64IZFINXZDINX: # %bb.0:
298-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
298+
; RV64IZFINXZDINX-NEXT: frflags a2
299299
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
300-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
300+
; RV64IZFINXZDINX-NEXT: fsflags a2
301301
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
302-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
302+
; RV64IZFINXZDINX-NEXT: frflags a2
303303
; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
304-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
304+
; RV64IZFINXZDINX-NEXT: fsflags a2
305305
; RV64IZFINXZDINX-NEXT: or a2, a4, a3
306306
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
307307
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -430,13 +430,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
430430
;
431431
; RV32IZFINXZDINX-LABEL: fcmp_ueq:
432432
; RV32IZFINXZDINX: # %bb.0:
433-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
433+
; RV32IZFINXZDINX-NEXT: frflags a4
434434
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
435-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
435+
; RV32IZFINXZDINX-NEXT: fsflags a4
436436
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
437-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
437+
; RV32IZFINXZDINX-NEXT: frflags a4
438438
; RV32IZFINXZDINX-NEXT: flt.d a6, a2, a0
439-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
439+
; RV32IZFINXZDINX-NEXT: fsflags a4
440440
; RV32IZFINXZDINX-NEXT: or a4, a6, a5
441441
; RV32IZFINXZDINX-NEXT: xori a4, a4, 1
442442
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
@@ -445,13 +445,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind strictfp {
445445
;
446446
; RV64IZFINXZDINX-LABEL: fcmp_ueq:
447447
; RV64IZFINXZDINX: # %bb.0:
448-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
448+
; RV64IZFINXZDINX-NEXT: frflags a2
449449
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
450-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
450+
; RV64IZFINXZDINX-NEXT: fsflags a2
451451
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
452-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
452+
; RV64IZFINXZDINX-NEXT: frflags a2
453453
; RV64IZFINXZDINX-NEXT: flt.d a4, a1, a0
454-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
454+
; RV64IZFINXZDINX-NEXT: fsflags a2
455455
; RV64IZFINXZDINX-NEXT: or a3, a4, a3
456456
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
457457
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
@@ -528,19 +528,19 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind strictfp {
528528
;
529529
; RV32IZFINXZDINX-LABEL: fcmp_ugt:
530530
; RV32IZFINXZDINX: # %bb.0:
531-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
531+
; RV32IZFINXZDINX-NEXT: frflags a4
532532
; RV32IZFINXZDINX-NEXT: fle.d a5, a0, a2
533-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
533+
; RV32IZFINXZDINX-NEXT: fsflags a4
534534
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
535535
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
536536
; RV32IZFINXZDINX-NEXT: mv a0, a4
537537
; RV32IZFINXZDINX-NEXT: ret
538538
;
539539
; RV64IZFINXZDINX-LABEL: fcmp_ugt:
540540
; RV64IZFINXZDINX: # %bb.0:
541-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
541+
; RV64IZFINXZDINX-NEXT: frflags a2
542542
; RV64IZFINXZDINX-NEXT: fle.d a3, a0, a1
543-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
543+
; RV64IZFINXZDINX-NEXT: fsflags a2
544544
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
545545
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
546546
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -582,19 +582,19 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp {
582582
;
583583
; RV32IZFINXZDINX-LABEL: fcmp_uge:
584584
; RV32IZFINXZDINX: # %bb.0:
585-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
585+
; RV32IZFINXZDINX-NEXT: frflags a4
586586
; RV32IZFINXZDINX-NEXT: flt.d a5, a0, a2
587-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
587+
; RV32IZFINXZDINX-NEXT: fsflags a4
588588
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
589589
; RV32IZFINXZDINX-NEXT: feq.d zero, a0, a2
590590
; RV32IZFINXZDINX-NEXT: mv a0, a4
591591
; RV32IZFINXZDINX-NEXT: ret
592592
;
593593
; RV64IZFINXZDINX-LABEL: fcmp_uge:
594594
; RV64IZFINXZDINX: # %bb.0:
595-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
595+
; RV64IZFINXZDINX-NEXT: frflags a2
596596
; RV64IZFINXZDINX-NEXT: flt.d a3, a0, a1
597-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
597+
; RV64IZFINXZDINX-NEXT: fsflags a2
598598
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
599599
; RV64IZFINXZDINX-NEXT: feq.d zero, a0, a1
600600
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -638,19 +638,19 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp {
638638
;
639639
; RV32IZFINXZDINX-LABEL: fcmp_ult:
640640
; RV32IZFINXZDINX: # %bb.0:
641-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
641+
; RV32IZFINXZDINX-NEXT: frflags a4
642642
; RV32IZFINXZDINX-NEXT: fle.d a5, a2, a0
643-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
643+
; RV32IZFINXZDINX-NEXT: fsflags a4
644644
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
645645
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
646646
; RV32IZFINXZDINX-NEXT: mv a0, a4
647647
; RV32IZFINXZDINX-NEXT: ret
648648
;
649649
; RV64IZFINXZDINX-LABEL: fcmp_ult:
650650
; RV64IZFINXZDINX: # %bb.0:
651-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
651+
; RV64IZFINXZDINX-NEXT: frflags a2
652652
; RV64IZFINXZDINX-NEXT: fle.d a3, a1, a0
653-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
653+
; RV64IZFINXZDINX-NEXT: fsflags a2
654654
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
655655
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
656656
; RV64IZFINXZDINX-NEXT: mv a0, a2
@@ -692,19 +692,19 @@ define i32 @fcmp_ule(double %a, double %b) nounwind strictfp {
692692
;
693693
; RV32IZFINXZDINX-LABEL: fcmp_ule:
694694
; RV32IZFINXZDINX: # %bb.0:
695-
; RV32IZFINXZDINX-NEXT: csrr a4, fflags
695+
; RV32IZFINXZDINX-NEXT: frflags a4
696696
; RV32IZFINXZDINX-NEXT: flt.d a5, a2, a0
697-
; RV32IZFINXZDINX-NEXT: csrw fflags, a4
697+
; RV32IZFINXZDINX-NEXT: fsflags a4
698698
; RV32IZFINXZDINX-NEXT: xori a4, a5, 1
699699
; RV32IZFINXZDINX-NEXT: feq.d zero, a2, a0
700700
; RV32IZFINXZDINX-NEXT: mv a0, a4
701701
; RV32IZFINXZDINX-NEXT: ret
702702
;
703703
; RV64IZFINXZDINX-LABEL: fcmp_ule:
704704
; RV64IZFINXZDINX: # %bb.0:
705-
; RV64IZFINXZDINX-NEXT: csrr a2, fflags
705+
; RV64IZFINXZDINX-NEXT: frflags a2
706706
; RV64IZFINXZDINX-NEXT: flt.d a3, a1, a0
707-
; RV64IZFINXZDINX-NEXT: csrw fflags, a2
707+
; RV64IZFINXZDINX-NEXT: fsflags a2
708708
; RV64IZFINXZDINX-NEXT: xori a2, a3, 1
709709
; RV64IZFINXZDINX-NEXT: feq.d zero, a1, a0
710710
; RV64IZFINXZDINX-NEXT: mv a0, a2

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