Use 2 byte loads for FP16 arguments

Author: ostannard

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -4765,17 +4765,18 @@ SDValue ARMTargetLowering::LowerFormalArguments(
             // a 4 byte stack slot. This is done as-if the extension was done
             // in a 32-bit register, so the actual bytes used for the value
             // differ between little and big endian.
+            assert(VA.getLocVT().getSizeInBits() == 32);
             unsigned FIOffset = VA.getLocMemOffset();
             int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits() / 8,
                                            FIOffset, true);
 
-            // Create load nodes to retrieve arguments from the stack.
-            SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
-            SDValue Load = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
-                                       MachinePointerInfo::getFixedStack(
-                                           DAG.getMachineFunction(), FI));
-            InVals.push_back(
-                MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Load));
+            SDValue Addr = DAG.getFrameIndex(FI, PtrVT);
+            if (DAG.getDataLayout().isBigEndian())
+              Addr = DAG.getObjectPtrOffset(dl, Addr, TypeSize::getFixed(2));
+
+            InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, Addr,
+                                         MachinePointerInfo::getFixedStack(
+                                             DAG.getMachineFunction(), FI)));
 
           } else {
             unsigned FIOffset = VA.getLocMemOffset();

llvm/test/CodeGen/Thumb2/fp16-pcs.ll

@@ -78,15 +78,13 @@ define arm_aapcscc half @callee_soft_half_on_stack(float %r0, float %r1, float %
 ;
 ; LE-FP16-LABEL: callee_soft_half_on_stack:
 ; LE-FP16:       @ %bb.0: @ %entry
-; LE-FP16-NEXT:    ldr r0, [sp]
-; LE-FP16-NEXT:    vmov.f16 s0, r0
+; LE-FP16-NEXT:    vldr.16 s0, [sp]
 ; LE-FP16-NEXT:    vmov r0, s0
 ; LE-FP16-NEXT:    bx lr
 ;
 ; BE-FP16-LABEL: callee_soft_half_on_stack:
 ; BE-FP16:       @ %bb.0: @ %entry
-; BE-FP16-NEXT:    ldr r0, [sp]
-; BE-FP16-NEXT:    vmov.f16 s0, r0
+; BE-FP16-NEXT:    vldr.16 s0, [sp, #2]
 ; BE-FP16-NEXT:    vmov r0, s0
 ; BE-FP16-NEXT:    bx lr
 entry:
@@ -224,14 +222,12 @@ define arm_aapcs_vfpcc half @callee_hard_half_on_stack(float %s0, float %s1, flo
 ;
 ; LE-FP16-LABEL: callee_hard_half_on_stack:
 ; LE-FP16:       @ %bb.0: @ %entry
-; LE-FP16-NEXT:    ldr r0, [sp]
-; LE-FP16-NEXT:    vmov.f16 s0, r0
+; LE-FP16-NEXT:    vldr.16 s0, [sp]
 ; LE-FP16-NEXT:    bx lr
 ;
 ; BE-FP16-LABEL: callee_hard_half_on_stack:
 ; BE-FP16:       @ %bb.0: @ %entry
-; BE-FP16-NEXT:    ldr r0, [sp]
-; BE-FP16-NEXT:    vmov.f16 s0, r0
+; BE-FP16-NEXT:    vldr.16 s0, [sp, #2]
 ; BE-FP16-NEXT:    bx lr
 entry:
   ret half %f