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[AVR] Convert tests to opaque pointers (NFC)
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53 files changed

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‎llvm/test/CodeGen/AVR/PR37143.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44
; CHECK: ldd {{r[0-9]+}}, [[PTR]]+1
55
; CHECK: std [[PTR2:[XYZ]]]+1, {{r[0-9]+}}
66
; CHECK: st [[PTR2]], {{r[0-9]+}}
7-
define void @load_store_16(i16* nocapture %ptr) local_unnamed_addr #1 {
7+
define void @load_store_16(ptr nocapture %ptr) local_unnamed_addr #1 {
88
entry:
9-
%0 = load i16, i16* %ptr, align 2
9+
%0 = load i16, ptr %ptr, align 2
1010
%add = add i16 %0, 5
11-
store i16 %add, i16* %ptr, align 2
11+
store i16 %add, ptr %ptr, align 2
1212
ret void
1313
}

‎llvm/test/CodeGen/AVR/alloca.ll‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
22

3-
declare i16 @allocate(i16*, i16*)
3+
declare i16 @allocate(ptr, ptr)
44

55
; Test taking an address of an alloca with a small offset (adiw)
66
define i16 @alloca_addressof_small() {
@@ -18,9 +18,9 @@ entry:
1818
; CHECK: pop r28
1919
%p = alloca [18 x i16]
2020
%k = alloca [14 x i16]
21-
%arrayidx = getelementptr inbounds [14 x i16], [14 x i16]* %k, i16 0, i16 8
22-
%arrayidx1 = getelementptr inbounds [18 x i16], [18 x i16]* %p, i16 0, i16 5
23-
%call = call i16 @allocate(i16* %arrayidx, i16* %arrayidx1)
21+
%arrayidx = getelementptr inbounds [14 x i16], ptr %k, i16 0, i16 8
22+
%arrayidx1 = getelementptr inbounds [18 x i16], ptr %p, i16 0, i16 5
23+
%call = call i16 @allocate(ptr %arrayidx, ptr %arrayidx1)
2424
ret i16 %call
2525
}
2626

@@ -35,9 +35,9 @@ entry:
3535
; CHECK: sbci r23, 255
3636
%p = alloca [55 x i16]
3737
%k = alloca [14 x i16]
38-
%arrayidx = getelementptr inbounds [14 x i16], [14 x i16]* %k, i16 0, i16 8
39-
%arrayidx1 = getelementptr inbounds [55 x i16], [55 x i16]* %p, i16 0, i16 41
40-
%call = call i16 @allocate(i16* %arrayidx, i16* %arrayidx1)
38+
%arrayidx = getelementptr inbounds [14 x i16], ptr %k, i16 0, i16 8
39+
%arrayidx1 = getelementptr inbounds [55 x i16], ptr %p, i16 0, i16 41
40+
%call = call i16 @allocate(ptr %arrayidx, ptr %arrayidx1)
4141
ret i16 %call
4242
}
4343

@@ -55,13 +55,13 @@ entry:
5555
; CHECK: sbiw r28, 57
5656
%p = alloca [15 x i16]
5757
%k = alloca [14 x i16]
58-
%arrayidx = getelementptr inbounds [15 x i16], [15 x i16]* %p, i16 0, i16 45
59-
store i16 22, i16* %arrayidx
60-
%arrayidx1 = getelementptr inbounds [14 x i16], [14 x i16]* %k, i16 0, i16 11
61-
store i16 42, i16* %arrayidx1
62-
%arrayidx2 = getelementptr inbounds [14 x i16], [14 x i16]* %k, i16 0, i16 0
63-
%arrayidx3 = getelementptr inbounds [15 x i16], [15 x i16]* %p, i16 0, i16 0
64-
%call = call i16 @allocate(i16* %arrayidx2, i16* %arrayidx3)
58+
%arrayidx = getelementptr inbounds [15 x i16], ptr %p, i16 0, i16 45
59+
store i16 22, ptr %arrayidx
60+
%arrayidx1 = getelementptr inbounds [14 x i16], ptr %k, i16 0, i16 11
61+
store i16 42, ptr %arrayidx1
62+
%arrayidx2 = getelementptr inbounds [14 x i16], ptr %k, i16 0, i16 0
63+
%arrayidx3 = getelementptr inbounds [15 x i16], ptr %p, i16 0, i16 0
64+
%call = call i16 @allocate(ptr %arrayidx2, ptr %arrayidx3)
6565
ret i16 %call
6666
}
6767

@@ -76,9 +76,9 @@ define void @alloca_write_huge() {
7676
; CHECK: subi r28, 215
7777
; CHECK: sbci r29, 0
7878
%k = alloca [140 x i16]
79-
%arrayidx = getelementptr inbounds [140 x i16], [140 x i16]* %k, i16 0, i16 138
80-
store i16 22, i16* %arrayidx
81-
%arraydecay = getelementptr inbounds [140 x i16], [140 x i16]* %k, i16 0, i16 0
82-
call i16 @allocate(i16* %arraydecay, i16* null)
79+
%arrayidx = getelementptr inbounds [140 x i16], ptr %k, i16 0, i16 138
80+
store i16 22, ptr %arrayidx
81+
%arraydecay = getelementptr inbounds [140 x i16], ptr %k, i16 0, i16 0
82+
call i16 @allocate(ptr %arraydecay, ptr null)
8383
ret void
8484
}

‎llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,13 @@
1111
%UnsafeCell = type { i16, [0 x i8] }
1212

1313
; CHECK-LABEL: foo
14-
define i8 @foo(%AtomicI16*) {
14+
define i8 @foo(ptr) {
1515
start:
1616

1717
; We should not be generating atomics that use the X register, they will fail when emitting MC.
1818
; CHECK-NOT: X
19-
%1 = getelementptr inbounds %AtomicI16, %AtomicI16* %0, i16 0, i32 0, i32 0
20-
%2 = load atomic i16, i16* %1 seq_cst, align 2
19+
%1 = getelementptr inbounds %AtomicI16, ptr %0, i16 0, i32 0, i32 0
20+
%2 = load atomic i16, ptr %1 seq_cst, align 2
2121
ret i8 0
2222
}
2323

‎llvm/test/CodeGen/AVR/atomics/load16.ll‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -6,22 +6,22 @@
66
; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
77
; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD]]+1
88
; CHECK-NEXT: out 63, r0
9-
define i16 @atomic_load16(i16* %foo) {
10-
%val = load atomic i16, i16* %foo unordered, align 2
9+
define i16 @atomic_load16(ptr %foo) {
10+
%val = load atomic i16, ptr %foo unordered, align 2
1111
ret i16 %val
1212
}
1313

1414
; CHECK-LABEL: atomic_load_swap16
1515
; CHECK: call __sync_lock_test_and_set_2
16-
define i16 @atomic_load_swap16(i16* %foo) {
17-
%val = atomicrmw xchg i16* %foo, i16 13 seq_cst
16+
define i16 @atomic_load_swap16(ptr %foo) {
17+
%val = atomicrmw xchg ptr %foo, i16 13 seq_cst
1818
ret i16 %val
1919
}
2020

2121
; CHECK-LABEL: atomic_load_cmp_swap16
2222
; CHECK: call __sync_val_compare_and_swap_2
23-
define i16 @atomic_load_cmp_swap16(i16* %foo) {
24-
%val = cmpxchg i16* %foo, i16 5, i16 10 acq_rel monotonic
23+
define i16 @atomic_load_cmp_swap16(ptr %foo) {
24+
%val = cmpxchg ptr %foo, i16 5, i16 10 acq_rel monotonic
2525
%value_loaded = extractvalue { i16, i1 } %val, 0
2626
ret i16 %value_loaded
2727
}
@@ -36,8 +36,8 @@ define i16 @atomic_load_cmp_swap16(i16* %foo) {
3636
; CHECK-NEXT: std [[RR]]+1, [[RR1H]]
3737
; CHECK-NEXT: st [[RR]], [[RR1L]]
3838
; CHECK-NEXT: out 63, r0
39-
define i16 @atomic_load_add16(i16* %foo) {
40-
%val = atomicrmw add i16* %foo, i16 13 seq_cst
39+
define i16 @atomic_load_add16(ptr %foo) {
40+
%val = atomicrmw add ptr %foo, i16 13 seq_cst
4141
ret i16 %val
4242
}
4343

@@ -52,8 +52,8 @@ define i16 @atomic_load_add16(i16* %foo) {
5252
; CHECK-NEXT: std [[RR]]+1, [[TMPH]]
5353
; CHECK-NEXT: st [[RR]], [[TMPL]]
5454
; CHECK-NEXT: out 63, r0
55-
define i16 @atomic_load_sub16(i16* %foo) {
56-
%val = atomicrmw sub i16* %foo, i16 13 seq_cst
55+
define i16 @atomic_load_sub16(ptr %foo) {
56+
%val = atomicrmw sub ptr %foo, i16 13 seq_cst
5757
ret i16 %val
5858
}
5959

@@ -67,8 +67,8 @@ define i16 @atomic_load_sub16(i16* %foo) {
6767
; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
6868
; CHECK-NEXT: st [[RR]], [[RD1L]]
6969
; CHECK-NEXT: out 63, r0
70-
define i16 @atomic_load_and16(i16* %foo) {
71-
%val = atomicrmw and i16* %foo, i16 13 seq_cst
70+
define i16 @atomic_load_and16(ptr %foo) {
71+
%val = atomicrmw and ptr %foo, i16 13 seq_cst
7272
ret i16 %val
7373
}
7474

@@ -82,8 +82,8 @@ define i16 @atomic_load_and16(i16* %foo) {
8282
; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
8383
; CHECK-NEXT: st [[RR]], [[RD1L]]
8484
; CHECK-NEXT: out 63, r0
85-
define i16 @atomic_load_or16(i16* %foo) {
86-
%val = atomicrmw or i16* %foo, i16 13 seq_cst
85+
define i16 @atomic_load_or16(ptr %foo) {
86+
%val = atomicrmw or ptr %foo, i16 13 seq_cst
8787
ret i16 %val
8888
}
8989

@@ -97,42 +97,42 @@ define i16 @atomic_load_or16(i16* %foo) {
9797
; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
9898
; CHECK-NEXT: st [[RR]], [[RD1L]]
9999
; CHECK-NEXT: out 63, r0
100-
define i16 @atomic_load_xor16(i16* %foo) {
101-
%val = atomicrmw xor i16* %foo, i16 13 seq_cst
100+
define i16 @atomic_load_xor16(ptr %foo) {
101+
%val = atomicrmw xor ptr %foo, i16 13 seq_cst
102102
ret i16 %val
103103
}
104104

105105
; CHECK-LABEL: atomic_load_nand16
106106
; CHECK: call __sync_fetch_and_nand_2
107-
define i16 @atomic_load_nand16(i16* %foo) {
108-
%val = atomicrmw nand i16* %foo, i16 13 seq_cst
107+
define i16 @atomic_load_nand16(ptr %foo) {
108+
%val = atomicrmw nand ptr %foo, i16 13 seq_cst
109109
ret i16 %val
110110
}
111111

112112
; CHECK-LABEL: atomic_load_max16
113113
; CHECK: call __sync_fetch_and_max_2
114-
define i16 @atomic_load_max16(i16* %foo) {
115-
%val = atomicrmw max i16* %foo, i16 13 seq_cst
114+
define i16 @atomic_load_max16(ptr %foo) {
115+
%val = atomicrmw max ptr %foo, i16 13 seq_cst
116116
ret i16 %val
117117
}
118118

119119
; CHECK-LABEL: atomic_load_min16
120120
; CHECK: call __sync_fetch_and_min_2
121-
define i16 @atomic_load_min16(i16* %foo) {
122-
%val = atomicrmw min i16* %foo, i16 13 seq_cst
121+
define i16 @atomic_load_min16(ptr %foo) {
122+
%val = atomicrmw min ptr %foo, i16 13 seq_cst
123123
ret i16 %val
124124
}
125125

126126
; CHECK-LABEL: atomic_load_umax16
127127
; CHECK: call __sync_fetch_and_umax_2
128-
define i16 @atomic_load_umax16(i16* %foo) {
129-
%val = atomicrmw umax i16* %foo, i16 13 seq_cst
128+
define i16 @atomic_load_umax16(ptr %foo) {
129+
%val = atomicrmw umax ptr %foo, i16 13 seq_cst
130130
ret i16 %val
131131
}
132132

133133
; CHECK-LABEL: atomic_load_umin16
134134
; CHECK: call __sync_fetch_and_umin_2
135-
define i16 @atomic_load_umin16(i16* %foo) {
136-
%val = atomicrmw umin i16* %foo, i16 13 seq_cst
135+
define i16 @atomic_load_umin16(ptr %foo) {
136+
%val = atomicrmw umin ptr %foo, i16 13 seq_cst
137137
ret i16 %val
138138
}

‎llvm/test/CodeGen/AVR/atomics/load32.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,15 @@
22

33
; CHECK-LABEL: atomic_load32
44
; CHECK: call __sync_val_compare_and_swap_4
5-
define i32 @atomic_load32(i32* %foo) {
6-
%val = load atomic i32, i32* %foo unordered, align 4
5+
define i32 @atomic_load32(ptr %foo) {
6+
%val = load atomic i32, ptr %foo unordered, align 4
77
ret i32 %val
88
}
99

1010
; CHECK-LABEL: atomic_load_sub32
1111
; CHECK: call __sync_fetch_and_sub_4
12-
define i32 @atomic_load_sub32(i32* %foo) {
13-
%val = atomicrmw sub i32* %foo, i32 13 seq_cst
12+
define i32 @atomic_load_sub32(ptr %foo) {
13+
%val = atomicrmw sub ptr %foo, i32 13 seq_cst
1414
ret i32 %val
1515
}
1616

‎llvm/test/CodeGen/AVR/atomics/load64.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,15 @@
22

33
; CHECK-LABEL: atomic_load64
44
; CHECK: call __sync_val_compare_and_swap_8
5-
define i64 @atomic_load64(i64* %foo) {
6-
%val = load atomic i64, i64* %foo unordered, align 8
5+
define i64 @atomic_load64(ptr %foo) {
6+
%val = load atomic i64, ptr %foo unordered, align 8
77
ret i64 %val
88
}
99

1010
; CHECK-LABEL: atomic_load_sub64
1111
; CHECK: call __sync_fetch_and_sub_8
12-
define i64 @atomic_load_sub64(i64* %foo) {
13-
%val = atomicrmw sub i64* %foo, i64 13 seq_cst
12+
define i64 @atomic_load_sub64(ptr %foo) {
13+
%val = atomicrmw sub ptr %foo, i64 13 seq_cst
1414
ret i64 %val
1515
}
1616

‎llvm/test/CodeGen/AVR/atomics/load8.ll‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -7,22 +7,22 @@
77
; CHECK-NEXT: cli
88
; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
99
; CHECK-NEXT: out 63, r0
10-
define i8 @atomic_load8(i8* %foo) {
11-
%val = load atomic i8, i8* %foo unordered, align 1
10+
define i8 @atomic_load8(ptr %foo) {
11+
%val = load atomic i8, ptr %foo unordered, align 1
1212
ret i8 %val
1313
}
1414

1515
; CHECK-LABEL: atomic_load_swap8
1616
; CHECK: call __sync_lock_test_and_set_1
17-
define i8 @atomic_load_swap8(i8* %foo) {
18-
%val = atomicrmw xchg i8* %foo, i8 13 seq_cst
17+
define i8 @atomic_load_swap8(ptr %foo) {
18+
%val = atomicrmw xchg ptr %foo, i8 13 seq_cst
1919
ret i8 %val
2020
}
2121

2222
; CHECK-LABEL: atomic_load_cmp_swap8
2323
; CHECK: call __sync_val_compare_and_swap_1
24-
define i8 @atomic_load_cmp_swap8(i8* %foo) {
25-
%val = cmpxchg i8* %foo, i8 5, i8 10 acq_rel monotonic
24+
define i8 @atomic_load_cmp_swap8(ptr %foo) {
25+
%val = cmpxchg ptr %foo, i8 5, i8 10 acq_rel monotonic
2626
%value_loaded = extractvalue { i8, i1 } %val, 0
2727
ret i8 %value_loaded
2828
}
@@ -34,8 +34,8 @@ define i8 @atomic_load_cmp_swap8(i8* %foo) {
3434
; CHECK-NEXT: add [[RR1:r[0-9]+]], [[RD]]
3535
; CHECK-NEXT: st [[RR]], [[RR1]]
3636
; CHECK-NEXT: out 63, r0
37-
define i8 @atomic_load_add8(i8* %foo) {
38-
%val = atomicrmw add i8* %foo, i8 13 seq_cst
37+
define i8 @atomic_load_add8(ptr %foo) {
38+
%val = atomicrmw add ptr %foo, i8 13 seq_cst
3939
ret i8 %val
4040
}
4141

@@ -47,8 +47,8 @@ define i8 @atomic_load_add8(i8* %foo) {
4747
; CHECK-NEXT: sub [[TMP]], [[RR1:r[0-9]+]]
4848
; CHECK-NEXT: st [[RR]], [[TMP]]
4949
; CHECK-NEXT: out 63, r0
50-
define i8 @atomic_load_sub8(i8* %foo) {
51-
%val = atomicrmw sub i8* %foo, i8 13 seq_cst
50+
define i8 @atomic_load_sub8(ptr %foo) {
51+
%val = atomicrmw sub ptr %foo, i8 13 seq_cst
5252
ret i8 %val
5353
}
5454

@@ -59,8 +59,8 @@ define i8 @atomic_load_sub8(i8* %foo) {
5959
; CHECK-NEXT: and [[RR1:r[0-9]+]], [[RD]]
6060
; CHECK-NEXT: st [[RR]], [[RR1]]
6161
; CHECK-NEXT: out 63, r0
62-
define i8 @atomic_load_and8(i8* %foo) {
63-
%val = atomicrmw and i8* %foo, i8 13 seq_cst
62+
define i8 @atomic_load_and8(ptr %foo) {
63+
%val = atomicrmw and ptr %foo, i8 13 seq_cst
6464
ret i8 %val
6565
}
6666

@@ -71,8 +71,8 @@ define i8 @atomic_load_and8(i8* %foo) {
7171
; CHECK-NEXT: or [[RR1:r[0-9]+]], [[RD]]
7272
; CHECK-NEXT: st [[RR]], [[RR1]]
7373
; CHECK-NEXT: out 63, r0
74-
define i8 @atomic_load_or8(i8* %foo) {
75-
%val = atomicrmw or i8* %foo, i8 13 seq_cst
74+
define i8 @atomic_load_or8(ptr %foo) {
75+
%val = atomicrmw or ptr %foo, i8 13 seq_cst
7676
ret i8 %val
7777
}
7878

@@ -83,43 +83,43 @@ define i8 @atomic_load_or8(i8* %foo) {
8383
; CHECK-NEXT: eor [[RR1:r[0-9]+]], [[RD]]
8484
; CHECK-NEXT: st [[RR]], [[RR1]]
8585
; CHECK-NEXT: out 63, r0
86-
define i8 @atomic_load_xor8(i8* %foo) {
87-
%val = atomicrmw xor i8* %foo, i8 13 seq_cst
86+
define i8 @atomic_load_xor8(ptr %foo) {
87+
%val = atomicrmw xor ptr %foo, i8 13 seq_cst
8888
ret i8 %val
8989
}
9090

9191
; CHECK-LABEL: atomic_load_nand8
9292
; CHECK: call __sync_fetch_and_nand_1
93-
define i8 @atomic_load_nand8(i8* %foo) {
94-
%val = atomicrmw nand i8* %foo, i8 13 seq_cst
93+
define i8 @atomic_load_nand8(ptr %foo) {
94+
%val = atomicrmw nand ptr %foo, i8 13 seq_cst
9595
ret i8 %val
9696
}
9797

9898
; CHECK-LABEL: atomic_load_max8
9999
; CHECK: call __sync_fetch_and_max_1
100-
define i8 @atomic_load_max8(i8* %foo) {
101-
%val = atomicrmw max i8* %foo, i8 13 seq_cst
100+
define i8 @atomic_load_max8(ptr %foo) {
101+
%val = atomicrmw max ptr %foo, i8 13 seq_cst
102102
ret i8 %val
103103
}
104104

105105
; CHECK-LABEL: atomic_load_min8
106106
; CHECK: call __sync_fetch_and_min_1
107-
define i8 @atomic_load_min8(i8* %foo) {
108-
%val = atomicrmw min i8* %foo, i8 13 seq_cst
107+
define i8 @atomic_load_min8(ptr %foo) {
108+
%val = atomicrmw min ptr %foo, i8 13 seq_cst
109109
ret i8 %val
110110
}
111111

112112
; CHECK-LABEL: atomic_load_umax8
113113
; CHECK: call __sync_fetch_and_umax_1
114-
define i8 @atomic_load_umax8(i8* %foo) {
115-
%val = atomicrmw umax i8* %foo, i8 13 seq_cst
114+
define i8 @atomic_load_umax8(ptr %foo) {
115+
%val = atomicrmw umax ptr %foo, i8 13 seq_cst
116116
ret i8 %val
117117
}
118118

119119
; CHECK-LABEL: atomic_load_umin8
120120
; CHECK: call __sync_fetch_and_umin_1
121-
define i8 @atomic_load_umin8(i8* %foo) {
122-
%val = atomicrmw umin i8* %foo, i8 13 seq_cst
121+
define i8 @atomic_load_umin8(ptr %foo) {
122+
%val = atomicrmw umin ptr %foo, i8 13 seq_cst
123123
ret i8 %val
124124
}
125125

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