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[RISCV] fix SP recovery in a function epilogue (#110809)
Currently, in the cases when fp register is presented and sp register is adjusted at the second time, sp recovery in a function epilogue isn't performed in the best way, for example: ``` lui a0, 2 sub sp, s0, a0 addi a0, a0, -2044 add sp, sp, a0 ``` This patch improves sp register recovery in such cases and the code snippet above becomes: ``` addi sp, s0, -2044 ```
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9 files changed

+91
-109
lines changed

9 files changed

+91
-109
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp‎

Lines changed: 66 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -755,6 +755,19 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
755755
}
756756
}
757757

758+
void RISCVFrameLowering::deallocateStack(MachineFunction &MF,
759+
MachineBasicBlock &MBB,
760+
MachineBasicBlock::iterator MBBI,
761+
const DebugLoc &DL, uint64_t StackSize,
762+
int64_t CFAOffset) const {
763+
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
764+
765+
Register SPReg = getSPReg(STI);
766+
767+
RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize),
768+
MachineInstr::FrameDestroy, getStackAlign());
769+
}
770+
758771
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
759772
MachineBasicBlock &MBB) const {
760773
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
@@ -786,20 +799,49 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
786799
--MBBI;
787800
}
788801

789-
const auto &CSI = getUnmanagedCSI(MF, MFI.getCalleeSavedInfo());
802+
const auto &CSI = MFI.getCalleeSavedInfo();
790803

791804
// Skip to before the restores of scalar callee-saved registers
792805
// FIXME: assumes exactly one instruction is used to restore each
793806
// callee-saved register.
794-
auto LastFrameDestroy = MBBI;
795-
if (!CSI.empty())
796-
LastFrameDestroy = std::prev(MBBI, CSI.size());
807+
auto LastFrameDestroy = std::prev(MBBI, getUnmanagedCSI(MF, CSI).size());
797808

798-
uint64_t RealStackSize = getStackSizeWithRVVPadding(MF);
799-
uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
800-
uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
809+
uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
810+
uint64_t RealStackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount
811+
: getStackSizeWithRVVPadding(MF);
812+
uint64_t StackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount
813+
: getStackSizeWithRVVPadding(MF) -
814+
RVFI->getReservedSpillsSize();
815+
uint64_t FPOffset = FirstSPAdjustAmount ? FirstSPAdjustAmount
816+
: getStackSizeWithRVVPadding(MF) -
817+
RVFI->getVarArgsSaveSize();
801818
uint64_t RVVStackSize = RVFI->getRVVStackSize();
802819

820+
bool RestoreFP = RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
821+
!hasReservedCallFrame(MF);
822+
823+
if (RVVStackSize) {
824+
// If RestoreFP the stack pointer will be restored using the frame pointer
825+
// value.
826+
if (!RestoreFP)
827+
adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
828+
MachineInstr::FrameDestroy);
829+
}
830+
831+
if (FirstSPAdjustAmount) {
832+
uint64_t SecondSPAdjustAmount =
833+
getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
834+
assert(SecondSPAdjustAmount > 0 &&
835+
"SecondSPAdjustAmount should be greater than zero");
836+
837+
// If RestoreFP the stack pointer will be restored using the frame pointer
838+
// value.
839+
if (!RestoreFP)
840+
RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg,
841+
StackOffset::getFixed(SecondSPAdjustAmount),
842+
MachineInstr::FrameDestroy, getStackAlign());
843+
}
844+
803845
// Restore the stack pointer using the value of the frame pointer. Only
804846
// necessary if the stack pointer was modified, meaning the stack size is
805847
// unknown.
@@ -810,50 +852,37 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
810852
// normally it's just checking the variable sized object is present or not
811853
// is enough, but we also don't preserve that at prologue/epilogue when
812854
// have vector objects in stack.
813-
if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
814-
!hasReservedCallFrame(MF)) {
855+
if (RestoreFP) {
815856
assert(hasFP(MF) && "frame pointer should not have been eliminated");
816-
RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg,
817-
StackOffset::getFixed(-FPOffset),
818-
MachineInstr::FrameDestroy, getStackAlign());
819-
} else {
820-
if (RVVStackSize)
821-
adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
822-
MachineInstr::FrameDestroy);
823-
}
824857

825-
uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
826-
if (FirstSPAdjustAmount) {
827-
uint64_t SecondSPAdjustAmount =
828-
getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
829-
assert(SecondSPAdjustAmount > 0 &&
830-
"SecondSPAdjustAmount should be greater than zero");
831-
832-
RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg,
833-
StackOffset::getFixed(SecondSPAdjustAmount),
834-
MachineInstr::FrameDestroy, getStackAlign());
858+
RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg,
859+
StackOffset::getFixed(-FPOffset), MachineInstr::FrameDestroy,
860+
getStackAlign());
835861
}
836862

837-
if (FirstSPAdjustAmount)
838-
StackSize = FirstSPAdjustAmount;
839-
840-
if (RVFI->isPushable(MF) && MBBI != MBB.end() &&
841-
MBBI->getOpcode() == RISCV::CM_POP) {
863+
bool ApplyPop = RVFI->isPushable(MF) && MBBI != MBB.end() &&
864+
MBBI->getOpcode() == RISCV::CM_POP;
865+
if (ApplyPop) {
842866
// Use available stack adjustment in pop instruction to deallocate stack
843867
// space. Align the stack size down to a multiple of 16. This is needed for
844868
// RVE.
845869
// FIXME: Can we increase the stack size to a multiple of 16 instead?
846870
uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
847871
MBBI->getOperand(1).setImm(Spimm);
848872
StackSize -= Spimm;
849-
}
850873

851-
// Deallocate stack
852-
if (StackSize != 0) {
853-
RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize),
854-
MachineInstr::FrameDestroy, getStackAlign());
874+
if (StackSize != 0)
875+
deallocateStack(MF, MBB, MBBI, DL, StackSize,
876+
/*stack_adj of cm.pop instr*/ RealStackSize - StackSize);
877+
878+
++MBBI;
855879
}
856880

881+
// Deallocate stack if we didn't already do it during cm.pop handling and
882+
// StackSize isn't a zero
883+
if (StackSize != 0 && !ApplyPop)
884+
deallocateStack(MF, MBB, MBBI, DL, StackSize, 0);
885+
857886
// Emit epilogue for shadow call stack.
858887
emitSCSEpilogue(MF, MBB, MBBI, DL);
859888
}

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,10 @@ class RISCVFrameLowering : public TargetFrameLowering {
9191
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
9292
MachineBasicBlock::iterator MI,
9393
bool HasFP) const;
94+
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
95+
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
96+
uint64_t StackSize, int64_t CFAOffset) const;
97+
9498
std::pair<int64_t, Align>
9599
assignRVVStackObjectOffsets(MachineFunction &MF) const;
96100
};

‎llvm/test/CodeGen/RISCV/branch-relaxation.ll‎

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -824,10 +824,7 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
824824
; CHECK-RV32-NEXT: #APP
825825
; CHECK-RV32-NEXT: # reg use t6
826826
; CHECK-RV32-NEXT: #NO_APP
827-
; CHECK-RV32-NEXT: lui a0, 2
828-
; CHECK-RV32-NEXT: sub sp, s0, a0
829-
; CHECK-RV32-NEXT: addi a0, a0, -2032
830-
; CHECK-RV32-NEXT: add sp, sp, a0
827+
; CHECK-RV32-NEXT: addi sp, s0, -2032
831828
; CHECK-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
832829
; CHECK-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
833830
; CHECK-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
@@ -1073,10 +1070,7 @@ define void @relax_jal_spill_32_adjust_spill_slot() {
10731070
; CHECK-RV64-NEXT: #APP
10741071
; CHECK-RV64-NEXT: # reg use t6
10751072
; CHECK-RV64-NEXT: #NO_APP
1076-
; CHECK-RV64-NEXT: lui a0, 2
1077-
; CHECK-RV64-NEXT: sub sp, s0, a0
1078-
; CHECK-RV64-NEXT: addiw a0, a0, -2032
1079-
; CHECK-RV64-NEXT: add sp, sp, a0
1073+
; CHECK-RV64-NEXT: addi sp, s0, -2032
10801074
; CHECK-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
10811075
; CHECK-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
10821076
; CHECK-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload
@@ -2323,10 +2317,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
23232317
; CHECK-RV32-NEXT: #APP
23242318
; CHECK-RV32-NEXT: # reg use t6
23252319
; CHECK-RV32-NEXT: #NO_APP
2326-
; CHECK-RV32-NEXT: lui a0, 2
2327-
; CHECK-RV32-NEXT: sub sp, s0, a0
2328-
; CHECK-RV32-NEXT: addi a0, a0, -2032
2329-
; CHECK-RV32-NEXT: add sp, sp, a0
2320+
; CHECK-RV32-NEXT: addi sp, s0, -2032
23302321
; CHECK-RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
23312322
; CHECK-RV32-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
23322323
; CHECK-RV32-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
@@ -2560,10 +2551,7 @@ define void @relax_jal_spill_64_adjust_spill_slot() {
25602551
; CHECK-RV64-NEXT: #APP
25612552
; CHECK-RV64-NEXT: # reg use t6
25622553
; CHECK-RV64-NEXT: #NO_APP
2563-
; CHECK-RV64-NEXT: lui a0, 2
2564-
; CHECK-RV64-NEXT: sub sp, s0, a0
2565-
; CHECK-RV64-NEXT: addiw a0, a0, -2032
2566-
; CHECK-RV64-NEXT: add sp, sp, a0
2554+
; CHECK-RV64-NEXT: addi sp, s0, -2032
25672555
; CHECK-RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
25682556
; CHECK-RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
25692557
; CHECK-RV64-NEXT: ld s1, 2008(sp) # 8-byte Folded Reload

‎llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -41,10 +41,7 @@
4141
; CHECK-NEXT: sd a0, -8(a1)
4242
; CHECK-NEXT: ld a1, 0(sp)
4343
; CHECK-NEXT: call foo
44-
; CHECK-NEXT: lui a0, 2
45-
; CHECK-NEXT: sub sp, s0, a0
46-
; CHECK-NEXT: addiw a0, a0, -2032
47-
; CHECK-NEXT: add sp, sp, a0
44+
; CHECK-NEXT: addi sp, s0, -2032
4845
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
4946
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
5047
; CHECK-NEXT: addi sp, sp, 2032

‎llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,7 @@ body: |
4646
; CHECK-NEXT: $x10 = ADDI killed $x10, -2048
4747
; CHECK-NEXT: $x10 = ADDI killed $x10, -224
4848
; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10
49-
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
50-
; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -224
51-
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240
49+
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2032
5250
; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
5351
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
5452
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032

‎llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -109,9 +109,7 @@ define riscv_vector_cc void @local_stack_allocation_frame_pointer() "frame-point
109109
; SPILL-O2-NEXT: addi sp, sp, -480
110110
; SPILL-O2-NEXT: lbu a0, -1912(s0)
111111
; SPILL-O2-NEXT: sb a0, -1912(s0)
112-
; SPILL-O2-NEXT: addi sp, s0, -2048
113-
; SPILL-O2-NEXT: addi sp, sp, -464
114-
; SPILL-O2-NEXT: addi sp, sp, 480
112+
; SPILL-O2-NEXT: addi sp, s0, -2032
115113
; SPILL-O2-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
116114
; SPILL-O2-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
117115
; SPILL-O2-NEXT: addi sp, sp, 2032

‎llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -150,9 +150,7 @@ body: |
150150
; CHECK-NEXT: PseudoBR %bb.2
151151
; CHECK-NEXT: {{ $}}
152152
; CHECK-NEXT: bb.2:
153-
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
154-
; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -256
155-
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 272
153+
; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2032
156154
; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
157155
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
158156
; CHECK-NEXT: $x18 = LD $x2, 2008 :: (load (s64) from %stack.5)

‎llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,7 @@
3333
; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
3434
; CHECK-NEXT: ld a0, 8(sp)
3535
; CHECK-NEXT: call spillslot
36-
; CHECK-NEXT: addi sp, s0, -2048
37-
; CHECK-NEXT: addi sp, sp, -256
38-
; CHECK-NEXT: addi sp, sp, 272
36+
; CHECK-NEXT: addi sp, s0, -2032
3937
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
4038
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
4139
; CHECK-NEXT: addi sp, sp, 2032

‎llvm/test/CodeGen/RISCV/stack-realignment.ll‎

Lines changed: 12 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -815,8 +815,7 @@ define void @caller1024() {
815815
; RV32I-NEXT: andi sp, sp, -1024
816816
; RV32I-NEXT: addi a0, sp, 1024
817817
; RV32I-NEXT: call callee
818-
; RV32I-NEXT: addi sp, s0, -2048
819-
; RV32I-NEXT: addi sp, sp, 16
818+
; RV32I-NEXT: addi sp, s0, -2032
820819
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
821820
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
822821
; RV32I-NEXT: addi sp, sp, 2032
@@ -836,8 +835,7 @@ define void @caller1024() {
836835
; RV32I-ILP32E-NEXT: andi sp, sp, -1024
837836
; RV32I-ILP32E-NEXT: addi a0, sp, 1024
838837
; RV32I-ILP32E-NEXT: call callee
839-
; RV32I-ILP32E-NEXT: addi sp, s0, -2048
840-
; RV32I-ILP32E-NEXT: addi sp, sp, 4
838+
; RV32I-ILP32E-NEXT: addi sp, s0, -2044
841839
; RV32I-ILP32E-NEXT: lw ra, 2040(sp) # 4-byte Folded Reload
842840
; RV32I-ILP32E-NEXT: lw s0, 2036(sp) # 4-byte Folded Reload
843841
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
@@ -857,8 +855,7 @@ define void @caller1024() {
857855
; RV64I-NEXT: andi sp, sp, -1024
858856
; RV64I-NEXT: addi a0, sp, 1024
859857
; RV64I-NEXT: call callee
860-
; RV64I-NEXT: addi sp, s0, -2048
861-
; RV64I-NEXT: addi sp, sp, 16
858+
; RV64I-NEXT: addi sp, s0, -2032
862859
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
863860
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
864861
; RV64I-NEXT: addi sp, sp, 2032
@@ -878,8 +875,7 @@ define void @caller1024() {
878875
; RV64I-LP64E-NEXT: andi sp, sp, -1024
879876
; RV64I-LP64E-NEXT: addi a0, sp, 1024
880877
; RV64I-LP64E-NEXT: call callee
881-
; RV64I-LP64E-NEXT: addi sp, s0, -2048
882-
; RV64I-LP64E-NEXT: addi sp, sp, 8
878+
; RV64I-LP64E-NEXT: addi sp, s0, -2040
883879
; RV64I-LP64E-NEXT: ld ra, 2032(sp) # 8-byte Folded Reload
884880
; RV64I-LP64E-NEXT: ld s0, 2024(sp) # 8-byte Folded Reload
885881
; RV64I-LP64E-NEXT: addi sp, sp, 2040
@@ -959,10 +955,7 @@ define void @caller2048() {
959955
; RV32I-NEXT: addi a0, sp, 2047
960956
; RV32I-NEXT: addi a0, a0, 1
961957
; RV32I-NEXT: call callee
962-
; RV32I-NEXT: lui a0, 1
963-
; RV32I-NEXT: sub sp, s0, a0
964-
; RV32I-NEXT: addi sp, sp, 2032
965-
; RV32I-NEXT: addi sp, sp, 32
958+
; RV32I-NEXT: addi sp, s0, -2032
966959
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
967960
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
968961
; RV32I-NEXT: addi sp, sp, 2032
@@ -984,10 +977,7 @@ define void @caller2048() {
984977
; RV32I-ILP32E-NEXT: addi a0, sp, 2047
985978
; RV32I-ILP32E-NEXT: addi a0, a0, 1
986979
; RV32I-ILP32E-NEXT: call callee
987-
; RV32I-ILP32E-NEXT: lui a0, 1
988-
; RV32I-ILP32E-NEXT: sub sp, s0, a0
989-
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
990-
; RV32I-ILP32E-NEXT: addi sp, sp, 8
980+
; RV32I-ILP32E-NEXT: addi sp, s0, -2044
991981
; RV32I-ILP32E-NEXT: lw ra, 2040(sp) # 4-byte Folded Reload
992982
; RV32I-ILP32E-NEXT: lw s0, 2036(sp) # 4-byte Folded Reload
993983
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
@@ -1009,10 +999,7 @@ define void @caller2048() {
1009999
; RV64I-NEXT: addi a0, sp, 2047
10101000
; RV64I-NEXT: addi a0, a0, 1
10111001
; RV64I-NEXT: call callee
1012-
; RV64I-NEXT: lui a0, 1
1013-
; RV64I-NEXT: sub sp, s0, a0
1014-
; RV64I-NEXT: addi sp, sp, 2032
1015-
; RV64I-NEXT: addi sp, sp, 32
1002+
; RV64I-NEXT: addi sp, s0, -2032
10161003
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
10171004
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
10181005
; RV64I-NEXT: addi sp, sp, 2032
@@ -1034,10 +1021,7 @@ define void @caller2048() {
10341021
; RV64I-LP64E-NEXT: addi a0, sp, 2047
10351022
; RV64I-LP64E-NEXT: addi a0, a0, 1
10361023
; RV64I-LP64E-NEXT: call callee
1037-
; RV64I-LP64E-NEXT: lui a0, 1
1038-
; RV64I-LP64E-NEXT: sub sp, s0, a0
1039-
; RV64I-LP64E-NEXT: addi sp, sp, 2040
1040-
; RV64I-LP64E-NEXT: addi sp, sp, 16
1024+
; RV64I-LP64E-NEXT: addi sp, s0, -2040
10411025
; RV64I-LP64E-NEXT: ld ra, 2032(sp) # 8-byte Folded Reload
10421026
; RV64I-LP64E-NEXT: ld s0, 2024(sp) # 8-byte Folded Reload
10431027
; RV64I-LP64E-NEXT: addi sp, sp, 2040
@@ -1119,10 +1103,7 @@ define void @caller4096() {
11191103
; RV32I-NEXT: lui a0, 1
11201104
; RV32I-NEXT: add a0, sp, a0
11211105
; RV32I-NEXT: call callee
1122-
; RV32I-NEXT: lui a0, 2
1123-
; RV32I-NEXT: sub sp, s0, a0
1124-
; RV32I-NEXT: addi a0, a0, -2032
1125-
; RV32I-NEXT: add sp, sp, a0
1106+
; RV32I-NEXT: addi sp, s0, -2032
11261107
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
11271108
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
11281109
; RV32I-NEXT: addi sp, sp, 2032
@@ -1146,10 +1127,7 @@ define void @caller4096() {
11461127
; RV32I-ILP32E-NEXT: lui a0, 1
11471128
; RV32I-ILP32E-NEXT: add a0, sp, a0
11481129
; RV32I-ILP32E-NEXT: call callee
1149-
; RV32I-ILP32E-NEXT: lui a0, 2
1150-
; RV32I-ILP32E-NEXT: sub sp, s0, a0
1151-
; RV32I-ILP32E-NEXT: addi a0, a0, -2044
1152-
; RV32I-ILP32E-NEXT: add sp, sp, a0
1130+
; RV32I-ILP32E-NEXT: addi sp, s0, -2044
11531131
; RV32I-ILP32E-NEXT: lw ra, 2040(sp) # 4-byte Folded Reload
11541132
; RV32I-ILP32E-NEXT: lw s0, 2036(sp) # 4-byte Folded Reload
11551133
; RV32I-ILP32E-NEXT: addi sp, sp, 2044
@@ -1173,10 +1151,7 @@ define void @caller4096() {
11731151
; RV64I-NEXT: lui a0, 1
11741152
; RV64I-NEXT: add a0, sp, a0
11751153
; RV64I-NEXT: call callee
1176-
; RV64I-NEXT: lui a0, 2
1177-
; RV64I-NEXT: sub sp, s0, a0
1178-
; RV64I-NEXT: addiw a0, a0, -2032
1179-
; RV64I-NEXT: add sp, sp, a0
1154+
; RV64I-NEXT: addi sp, s0, -2032
11801155
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
11811156
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
11821157
; RV64I-NEXT: addi sp, sp, 2032
@@ -1200,10 +1175,7 @@ define void @caller4096() {
12001175
; RV64I-LP64E-NEXT: lui a0, 1
12011176
; RV64I-LP64E-NEXT: add a0, sp, a0
12021177
; RV64I-LP64E-NEXT: call callee
1203-
; RV64I-LP64E-NEXT: lui a0, 2
1204-
; RV64I-LP64E-NEXT: sub sp, s0, a0
1205-
; RV64I-LP64E-NEXT: addiw a0, a0, -2040
1206-
; RV64I-LP64E-NEXT: add sp, sp, a0
1178+
; RV64I-LP64E-NEXT: addi sp, s0, -2040
12071179
; RV64I-LP64E-NEXT: ld ra, 2032(sp) # 8-byte Folded Reload
12081180
; RV64I-LP64E-NEXT: ld s0, 2024(sp) # 8-byte Folded Reload
12091181
; RV64I-LP64E-NEXT: addi sp, sp, 2040

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