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Yuanke Luo
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[RegAlloc] Relax the split constrain on MMB prolog
https://reviews.llvm.org/D52052 is to prevent register split on the MBB which have prolog instructions defining the exec register (or mask register that activate the threads of a warp in GPU). The constrain seems too strict, because 1) If the split is allowed, it may fit the free live range of a physical register, and no spill will happen; 2) The register class of register that is under splitting may not be the same to the register that is defined in prolog, so there is no interference with the register being defined in prolog. The current code has another small issue. The MBB->getFirstNonDebugInstr() just skip debug instructions, but SA->getFirstSplitPoint(Number) would skip label and phi instructions. This cause some MBB with label instruction being taken as prolog. This patch is to relax the split constrain on MMB with prolog by checking if the register defined in prolog has the common register class with the register being split. It allow the split if the register defined in prolog is physical register or there is no common register class.
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-3245
lines changed

10 files changed

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-3245
lines changed

llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -773,8 +773,7 @@ bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
773773
// Abort if the spill cannot be inserted at the MBB' start
774774
if (((BC.Entry == SpillPlacement::MustSpill) ||
775775
(BC.Entry == SpillPlacement::PrefSpill)) &&
776-
SlotIndex::isEarlierInstr(BI.FirstInstr,
777-
SA->getFirstSplitPoint(BC.Number)))
776+
!SA->canSplitBeforeProlog(BC.Number))
778777
return false;
779778
}
780779

@@ -829,11 +828,7 @@ bool RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
829828
BCS[B].Number = Number;
830829

831830
// Abort if the spill cannot be inserted at the MBB' start
832-
MachineBasicBlock *MBB = MF->getBlockNumbered(Number);
833-
auto FirstNonDebugInstr = MBB->getFirstNonDebugInstr();
834-
if (FirstNonDebugInstr != MBB->end() &&
835-
SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*FirstNonDebugInstr),
836-
SA->getFirstSplitPoint(Number)))
831+
if (!SA->canSplitBeforeProlog(Number))
837832
return false;
838833
// Interference for the live-in value.
839834
if (Intf.first() <= Indexes->getMBBStartIdx(Number))

llvm/lib/CodeGen/SplitKit.cpp

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,34 @@ InsertPointAnalysis::getLastInsertPointIter(const LiveInterval &CurLI,
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return LIS.getInstructionFromIndex(LIP);
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}
149149

150+
bool InsertPointAnalysis::canSplitBeforeProlog(const LiveInterval &CurLI,
151+
const MachineBasicBlock &MBB) {
152+
const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo();
153+
154+
for (auto &MI : MBB) {
155+
if (MI.isPHI() || MI.isPosition() || MI.isDebugInstr() ||
156+
MI.isPseudoProbe())
157+
continue;
158+
159+
if (!TII->isBasicBlockPrologue(MI))
160+
return true;
161+
162+
for (auto &MO : MI.operands()) {
163+
if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
164+
continue;
165+
166+
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
167+
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
168+
const TargetRegisterClass *RC = MRI.getRegClass(MO.getReg());
169+
const TargetRegisterClass *CurRC = MRI.getRegClass(CurLI.reg());
170+
if (TRI->getCommonSubClass(RC, CurRC))
171+
return false;
172+
}
173+
}
174+
175+
return true;
176+
}
177+
150178
//===----------------------------------------------------------------------===//
151179
// Split Analysis
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//===----------------------------------------------------------------------===//

llvm/lib/CodeGen/SplitKit.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,9 @@ class LLVM_LIBRARY_VISIBILITY InsertPointAnalysis {
8989
return Res;
9090
}
9191

92+
/// Return true if we can split \pCurLI before \pMBB's prolog.
93+
bool canSplitBeforeProlog(const LiveInterval &CurLI,
94+
const MachineBasicBlock &MBB);
9295
};
9396

9497
/// SplitAnalysis - Analyze a LiveInterval, looking for live range splitting
@@ -247,6 +250,11 @@ class LLVM_LIBRARY_VISIBILITY SplitAnalysis {
247250
SlotIndex getFirstSplitPoint(unsigned Num) {
248251
return IPA.getFirstInsertPoint(*MF.getBlockNumbered(Num));
249252
}
253+
254+
bool canSplitBeforeProlog(unsigned Num) {
255+
MachineBasicBlock *BB = MF.getBlockNumbered(Num);
256+
return IPA.canSplitBeforeProlog(*CurLI, *BB);
257+
}
250258
};
251259

252260
/// SplitEditor - Edit machine code and LiveIntervals for live range

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