initial implementation

Author: RolandF77

llvm/include/llvm/IR/IntrinsicsPowerPC.td

@@ -1661,6 +1661,22 @@ let TargetPrefix = "ppc" in {
       DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty,
                              llvm_v1024i1_ty], [IntrNoMem]>;
 
+  def int_ppc_mma_dmxxextfdmr512 :
+      DefaultAttrsIntrinsic<[llvm_v256i1_ty, llvm_v256i1_ty], [llvm_v1024i1_ty,
+                             llvm_i32_ty], [IntrNoMem]>;
+
+  def int_ppc_mma_dmxxinstdmr512 :
+      DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty, llvm_v256i1_ty,
+                             llvm_v256i1_ty, llvm_i32_ty], [IntrNoMem]>;
+
+  def int_ppc_mma_dmxxextfdmr256 :
+      DefaultAttrsIntrinsic<[llvm_v256i1_ty], [llvm_v1024i1_ty, llvm_i32_ty],
+                            [IntrNoMem]>;
+
+  def int_ppc_mma_dmxxinstdmr256 :
+      DefaultAttrsIntrinsic<[llvm_v1024i1_ty], [llvm_v1024i1_ty, llvm_v256i1_ty,
+                             llvm_i32_ty], [IntrNoMem]>;
+
   // MMA Reduced-Precision: Outer Product Intrinsic Definitions.
   defm int_ppc_mma_xvi4ger8 :
         PowerPC_MMA_ACC_PP_Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty]>;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

@@ -135,6 +135,10 @@ MCRegister PPC::getRegNumForOperand(const MCInstrDesc &Desc, MCRegister Reg,
       if (PPC::isVRRegister(Reg))
 	return PPC::VSX32 + (Reg - PPC::V0);
       break;
+    case PPC::DMRROWpRCRegClassID: {
+      // Reference to dmr reg. There are four dmrrow pairs per dmr.
+      return PPC::DMR0 + ((Reg - PPC::DMRROWp0) / 4);
+    }
     // Other RegClass doesn't need mapping
     default:
       break;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -11146,6 +11146,102 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getMergeValues(RetOps, dl);
   }
 
+  case Intrinsic::ppc_mma_dmxxextfdmr512: {
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    assert(Idx && (Idx->getSExtValue() == 0 || Idx->getSExtValue() == 1) &&
+           "Specify P of 0 or 1 for lower or upper 512 bytes");
+    unsigned HiLo = Idx->getSExtValue();
+    unsigned Opcode;
+    unsigned Subx;
+    if (HiLo == 0) {
+      Opcode = PPC::DMXXEXTFDMR512;
+      Subx = PPC::sub_wacc_lo;
+    } else {
+      Opcode = PPC::DMXXEXTFDMR512_HI;
+      Subx = PPC::sub_wacc_hi;
+    }
+    SDValue Subreg(
+        DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
+                           Op.getOperand(1),
+                           DAG.getTargetConstant(Subx, dl, MVT::i32)),
+        0);
+    EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1};
+    return SDValue(DAG.getMachineNode(Opcode, dl, ReturnTypes, Subreg), 0);
+  }
+
+  case Intrinsic::ppc_mma_dmxxextfdmr256: {
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    assert(Idx && (Idx->getSExtValue() >= 0 || Idx->getSExtValue() <= 3) &&
+           "Specify a dmr row pair 0-3");
+    unsigned IdxVal = Idx->getSExtValue();
+    unsigned Pairx;
+    switch (IdxVal) {
+    case 0: Pairx = PPC::sub_dmrrowp0; break;
+    case 1: Pairx = PPC::sub_dmrrowp1; break;
+    case 2: Pairx = PPC::sub_wacc_hi_then_sub_dmrrowp0; break;
+    case 3: Pairx = PPC::sub_wacc_hi_then_sub_dmrrowp1; break;
+    }
+    SDValue Pair(
+        DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::v256i1,
+                           Op.getOperand(1),
+                           DAG.getTargetConstant(Pairx, dl, MVT::i32)),
+        0);
+    SDValue C = DAG.getTargetConstant(IdxVal, dl, MVT::i32);
+    return SDValue(
+        DAG.getMachineNode(PPC::DMXXEXTFDMR256, dl, MVT::v256i1, {Pair, C}), 0);
+  }
+
+  case Intrinsic::ppc_mma_dmxxinstdmr512: {
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(4));
+    assert(Idx && (Idx->getSExtValue() == 0 || Idx->getSExtValue() == 1) &&
+           "Specify P of 0 or 1 for lower or upper 512 bytes");
+    unsigned HiLo = Idx->getSExtValue();
+    unsigned Opcode;
+    unsigned Subx;
+    if (HiLo == 0) {
+      Opcode = PPC::DMXXINSTDMR512;
+      Subx = PPC::sub_wacc_lo;
+    } else {
+      Opcode = PPC::DMXXINSTDMR512_HI;
+      Subx = PPC::sub_wacc_hi;
+    }
+    SDValue Ops[] = { Op.getOperand(2), Op.getOperand(3) };
+    SDValue WideVec =
+        SDValue(DAG.getMachineNode(Opcode, dl, MVT::v512i1, Ops), 0);
+    SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
+    return
+        SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl,
+                                   MVT::v1024i1, Op.getOperand(1), WideVec,
+                                   SubReg),
+                0);
+  }
+
+  case Intrinsic::ppc_mma_dmxxinstdmr256: {
+    auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3));
+    assert(Idx && (Idx->getSExtValue() >= 0 || Idx->getSExtValue() <= 3) &&
+           "Specify a dmr row pair 0-3");
+    unsigned IdxVal = Idx->getSExtValue();
+    unsigned Pairx;
+    unsigned Subx;
+    switch (IdxVal) {
+    case 0: Subx = PPC::sub_dmrrowp0; break;
+    case 1: Subx = PPC::sub_dmrrowp1; break;
+    case 2: Subx = PPC::sub_wacc_hi_then_sub_dmrrowp0; break;
+    case 3: Subx = PPC::sub_wacc_hi_then_sub_dmrrowp1; break;
+    }
+    SDValue SubReg = DAG.getTargetConstant(Subx, dl, MVT::i32);
+    SDValue C = DAG.getTargetConstant(IdxVal, dl, MVT::i32);
+    SDValue Ops[] = { Op.getOperand(2), C };
+    SDValue WideVec =
+        SDValue(DAG.getMachineNode(PPC::DMXXINSTDMR256, dl, MVT::v512i1, Ops),
+                0);
+    return
+        SDValue(DAG.getMachineNode(PPC::INSERT_SUBREG, dl,
+                                   MVT::v1024i1, Op.getOperand(1), WideVec,
+                                   SubReg),
+                0);
+  }
+
   case Intrinsic::ppc_mma_xxmfacc:
   case Intrinsic::ppc_mma_xxmtacc: {
     // Allow pre-isa-future subtargets to lower as normal.