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Small change as previous changes made code not conform to
formatting standards.
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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24093,12 +24093,11 @@ static SDValue performMaskedGatherScatterCombine(
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SDLoc DL(HG);
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SDValue ExtOp = Index.getOperand(0);
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SDValue Ops[] = {HG->getChain(), HG->getInc(), HG->getMask(),
24096-
HG->getBasePtr(), ExtOp, HG->getScale(),
24097-
HG->getIntID()};
24098-
return DAG.getMaskedHistogram(DAG.getVTList(MVT::Other),
24099-
HG->getMemoryVT(), DL, Ops,
24100-
HG->getMemOperand(), HG->getIndexType());
24101-
24096+
HG->getBasePtr(), ExtOp, HG->getScale(),
24097+
HG->getIntID()};
24098+
return DAG.getMaskedHistogram(DAG.getVTList(MVT::Other), HG->getMemoryVT(),
24099+
DL, Ops, HG->getMemOperand(),
24100+
HG->getIndexType());
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}
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MaskedGatherScatterSDNode *MGS = cast<MaskedGatherScatterSDNode>(N);

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