whilewr/rw accept sme as well

SamTebbs33 · SamTebbs33 · commit 7ca41c89a3fd · 2025-08-15T16:56:00.000+01:00
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1001,6 +1001,7 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   }
   case Intrinsic::loop_dependence_raw_mask:
   case Intrinsic::loop_dependence_war_mask:
+    // The whilewr/rw instructions require SVE2
     if (ST->hasSVE2() || ST->hasSME())
       return 1;
     break;
@@ -5600,7 +5601,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
 
 bool AArch64TTIImpl::useSafeEltsMask() const {
   // The whilewr/rw instructions require SVE2
-  return ST->hasSVE2();
+  return ST->hasSVE2() || ST->hasSME();
 }
 
 InstructionCost

Original file line number	Diff line number	Diff line change
`@@ -1001,6 +1001,7 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,`
`1001`	`1001`	`}`
`1002`	`1002`	`case Intrinsic::loop_dependence_raw_mask:`
`1003`	`1003`	`case Intrinsic::loop_dependence_war_mask:`
	`1004`	`+ // The whilewr/rw instructions require SVE2`
`1004`	`1005`	`if (ST->hasSVE2() \|\| ST->hasSME())`
`1005`	`1006`	`return 1;`
`1006`	`1007`	`break;`
`@@ -5600,7 +5601,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(`
`5600`	`5601`
`5601`	`5602`	`bool AArch64TTIImpl::useSafeEltsMask() const {`
`5602`	`5603`	`// The whilewr/rw instructions require SVE2`
`5603`		`- return ST->hasSVE2();`
	`5604`	`+ return ST->hasSVE2() \|\| ST->hasSME();`
`5604`	`5605`	`}`
`5605`	`5606`
`5606`	`5607`	`InstructionCost`