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[X86] Remove unnecessary switch case
1 parent 696f3a5 commit 7caceb1

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+4
-14
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1 file changed

+4
-14
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 4 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -53743,21 +53743,12 @@ static SDValue combinei64TruncSrlConstant(SDValue N, EVT VT, SelectionDAG &DAG,
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SDValue Op = N.getOperand(0);
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APInt OpConst = Op.getConstantOperandAPInt(1);
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APInt SrlConst = N.getConstantOperandAPInt(1);
53746+
uint64_t SrlConstVal = SrlConst.getZExtValue();
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unsigned Opcode = Op.getOpcode();
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53748-
switch (Opcode) {
53749-
default:
53749+
if (SrlConst.ule(32) ||
53750+
(Opcode == ISD::ADD && OpConst.countr_zero() < SrlConstVal))
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return SDValue();
53751-
case ISD::ADD:
53752-
if (OpConst.countr_zero() < SrlConst.getZExtValue())
53753-
return SDValue();
53754-
[[fallthrough]];
53755-
case ISD::OR:
53756-
case ISD::XOR:
53757-
if (SrlConst.ule(32))
53758-
return SDValue();
53759-
break;
53760-
}
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SDValue OpLhsSrl =
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DAG.getNode(ISD::SRL, DL, MVT::i64, Op.getOperand(0), N.getOperand(1));
@@ -53766,8 +53757,7 @@ static SDValue combinei64TruncSrlConstant(SDValue N, EVT VT, SelectionDAG &DAG,
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APInt NewOpConstVal = OpConst.lshr(SrlConst).trunc(VT.getSizeInBits());
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SDValue NewOpConst = DAG.getConstant(NewOpConstVal, DL, VT);
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SDValue NewOpNode = DAG.getNode(Opcode, DL, VT, Trunc, NewOpConst);
53769-
EVT CleanUpVT =
53770-
EVT::getIntegerVT(*DAG.getContext(), 64 - SrlConst.getZExtValue());
53760+
EVT CleanUpVT = EVT::getIntegerVT(*DAG.getContext(), 64 - SrlConstVal);
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if (Opcode == ISD::ADD)
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return DAG.getZeroExtendInReg(NewOpNode, DL, CleanUpVT);

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