@@ -53743,21 +53743,12 @@ static SDValue combinei64TruncSrlConstant(SDValue N, EVT VT, SelectionDAG &DAG,
5374353743 SDValue Op = N.getOperand(0);
5374453744 APInt OpConst = Op.getConstantOperandAPInt(1);
5374553745 APInt SrlConst = N.getConstantOperandAPInt(1);
53746+ uint64_t SrlConstVal = SrlConst.getZExtValue();
5374653747 unsigned Opcode = Op.getOpcode();
5374753748
53748- switch (Opcode) {
53749- default:
53749+ if (SrlConst.ule(32) ||
53750+ (Opcode == ISD::ADD && OpConst.countr_zero() < SrlConstVal))
5375053751 return SDValue();
53751- case ISD::ADD:
53752- if (OpConst.countr_zero() < SrlConst.getZExtValue())
53753- return SDValue();
53754- [[fallthrough]];
53755- case ISD::OR:
53756- case ISD::XOR:
53757- if (SrlConst.ule(32))
53758- return SDValue();
53759- break;
53760- }
5376153752
5376253753 SDValue OpLhsSrl =
5376353754 DAG.getNode(ISD::SRL, DL, MVT::i64, Op.getOperand(0), N.getOperand(1));
@@ -53766,8 +53757,7 @@ static SDValue combinei64TruncSrlConstant(SDValue N, EVT VT, SelectionDAG &DAG,
5376653757 APInt NewOpConstVal = OpConst.lshr(SrlConst).trunc(VT.getSizeInBits());
5376753758 SDValue NewOpConst = DAG.getConstant(NewOpConstVal, DL, VT);
5376853759 SDValue NewOpNode = DAG.getNode(Opcode, DL, VT, Trunc, NewOpConst);
53769- EVT CleanUpVT =
53770- EVT::getIntegerVT(*DAG.getContext(), 64 - SrlConst.getZExtValue());
53760+ EVT CleanUpVT = EVT::getIntegerVT(*DAG.getContext(), 64 - SrlConstVal);
5377153761
5377253762 if (Opcode == ISD::ADD)
5377353763 return DAG.getZeroExtendInReg(NewOpNode, DL, CleanUpVT);
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