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[SLP]Check vector-like instruction for dominance in copyables
Need to check if the vector-like instruction is dominated by main operation in the copyables to prevent broken def-use chain Fixes #151456
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llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

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@@ -1329,7 +1329,7 @@ class InstructionsState {
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// If the copyable instructions comes after MainOp
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// (non-schedulable, but used in the block) - cannot vectorize
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// it, will possibly generate use before def.
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(isVectorLikeInstWithConstOps(I) || !MainOp->comesBefore(I)));
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!MainOp->comesBefore(I));
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};
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return IsNonSchedulableCopyableElement(V);
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@@ -0,0 +1,70 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define void @test(i32 %arg) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: i32 [[ARG:%.*]]) {
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; CHECK-NEXT: [[BB:.*]]:
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; CHECK-NEXT: br label %[[BB14:.*]]
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; CHECK: [[BB1:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <2 x i32> [[TMP11:%.*]], <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 1, i32 3>
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; CHECK-NEXT: br label %[[BB2:.*]]
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; CHECK: [[BB2]]:
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; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB14]] ], [ zeroinitializer, %[[BB1]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[BB14]] ], [ zeroinitializer, %[[BB1]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[BB14]] ], [ zeroinitializer, %[[BB1]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = phi <2 x i32> [ [[TMP11]], %[[BB14]] ], [ [[TMP0]], %[[BB1]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
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; CHECK-NEXT: [[ADD10:%.*]] = add i32 [[TMP5]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
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; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP7]], <2 x i32> <i32 2, i32 5>
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; CHECK-NEXT: br i1 false, label %[[BB14]], label %[[BB11:.*]]
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; CHECK: [[BB11]]:
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; CHECK-NEXT: [[TMP9:%.*]] = phi <2 x i32> [ [[TMP1]], %[[BB2]] ]
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; CHECK-NEXT: br label %[[BB14]]
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; CHECK: [[BB14]]:
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; CHECK-NEXT: [[PHI16:%.*]] = phi i32 [ [[ADD10]], %[[BB2]] ], [ 0, %[[BB]] ], [ 0, %[[BB11]] ]
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; CHECK-NEXT: [[PHI17:%.*]] = phi i32 [ [[TMP6]], %[[BB2]] ], [ 0, %[[BB]] ], [ 0, %[[BB11]] ]
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; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x i32> [ [[TMP8]], %[[BB2]] ], [ zeroinitializer, %[[BB]] ], [ zeroinitializer, %[[BB11]] ]
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; CHECK-NEXT: [[TMP11]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[ARG]], i32 1
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; CHECK-NEXT: switch i32 0, label %[[BB2]] [
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; CHECK-NEXT: i32 0, label %[[BB1]]
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; CHECK-NEXT: i32 1, label %[[BB1]]
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; CHECK-NEXT: ]
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;
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bb:
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br label %bb14
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bb1:
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%0 = shufflevector <2 x i32> %10, <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 1, i32 3>
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br label %bb2
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bb2:
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%1 = phi <2 x i32> [ zeroinitializer, %bb14 ], [ zeroinitializer, %bb1 ]
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%2 = phi <4 x i32> [ zeroinitializer, %bb14 ], [ zeroinitializer, %bb1 ]
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%3 = phi <4 x i32> [ zeroinitializer, %bb14 ], [ zeroinitializer, %bb1 ]
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%4 = phi <2 x i32> [ %10, %bb14 ], [ %0, %bb1 ]
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%5 = extractelement <4 x i32> %3, i32 3
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%add10 = add i32 %5, 0
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%6 = extractelement <2 x i32> %1, i32 1
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%7 = extractelement <4 x i32> %2, i32 2
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%8 = extractelement <2 x i32> %4, i32 1
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br i1 false, label %bb14, label %bb11
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bb11:
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%9 = phi <2 x i32> [ %1, %bb2 ]
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br label %bb14
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bb14:
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%phi15 = phi i32 [ %7, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
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%phi16 = phi i32 [ %add10, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
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%phi17 = phi i32 [ %6, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
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%phi18 = phi i32 [ %8, %bb2 ], [ 0, %bb ], [ 0, %bb11 ]
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%10 = insertelement <2 x i32> <i32 0, i32 poison>, i32 %arg, i32 1
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switch i32 0, label %bb2 [
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i32 0, label %bb1
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i32 1, label %bb1
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]
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}
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