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[X86] Tidyup up AVX512 FPCLASS instruction naming (#116661)
FPCLASS is a unary instruction with an immediate operand - update the naming to match similar instructions (e.g. VPSHUFD) by only using the source reg/mem and immediate in the instruction name
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7 files changed

+105
-105
lines changed

7 files changed

+105
-105
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -41,18 +41,18 @@ using namespace llvm;
4141
CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
4242

4343
#define CASE_FPCLASS_PACKED(Inst, src) \
44-
CASE_AVX_INS_COMMON(Inst, Z, r##src) \
45-
CASE_AVX_INS_COMMON(Inst, Z256, r##src) \
46-
CASE_AVX_INS_COMMON(Inst, Z128, r##src) \
47-
CASE_MASK_INS_COMMON(Inst, Z, r##src)
44+
CASE_AVX_INS_COMMON(Inst, Z, src##i) \
45+
CASE_AVX_INS_COMMON(Inst, Z256, src##i) \
46+
CASE_AVX_INS_COMMON(Inst, Z128, src##i) \
47+
CASE_MASK_INS_COMMON(Inst, Z, src##i)
4848

4949
#define CASE_FPCLASS_PACKED_MEM(Inst) \
5050
CASE_FPCLASS_PACKED(Inst, m) \
5151
CASE_FPCLASS_PACKED(Inst, mb)
5252

5353
#define CASE_FPCLASS_SCALAR(Inst, src) \
54-
CASE_AVX_INS_COMMON(Inst, Z, r##src) \
55-
CASE_MASK_INS_COMMON(Inst, Z, r##src)
54+
CASE_AVX_INS_COMMON(Inst, Z, src##i) \
55+
CASE_MASK_INS_COMMON(Inst, Z, src##i)
5656

5757
#define CASE_PTERNLOG(Inst, src) \
5858
CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \

‎llvm/lib/Target/X86/X86InstrAVX512.td‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2457,29 +2457,29 @@ multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr,
24572457
X86FoldableSchedWrite sched, X86VectorVTInfo _,
24582458
Predicate prd> {
24592459
let Predicates = [prd], ExeDomain = _.ExeDomain, Uses = [MXCSR] in {
2460-
def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2460+
def ri : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
24612461
(ins _.RC:$src1, i32u8imm:$src2),
24622462
OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24632463
[(set _.KRC:$dst,(X86Vfpclasss (_.VT _.RC:$src1),
24642464
(i32 timm:$src2)))]>,
24652465
Sched<[sched]>;
2466-
def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2466+
def rik : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
24672467
(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
24682468
OpcodeStr#_.Suffix#
24692469
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
24702470
[(set _.KRC:$dst,(and _.KRCWM:$mask,
24712471
(X86Vfpclasss_su (_.VT _.RC:$src1),
24722472
(i32 timm:$src2))))]>,
24732473
EVEX_K, Sched<[sched]>;
2474-
def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2474+
def mi : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
24752475
(ins _.IntScalarMemOp:$src1, i32u8imm:$src2),
24762476
OpcodeStr#_.Suffix#
24772477
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24782478
[(set _.KRC:$dst,
24792479
(X86Vfpclasss (_.ScalarIntMemFrags addr:$src1),
24802480
(i32 timm:$src2)))]>,
24812481
Sched<[sched.Folded, sched.ReadAfterFold]>;
2482-
def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2482+
def mik : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
24832483
(ins _.KRCWM:$mask, _.IntScalarMemOp:$src1, i32u8imm:$src2),
24842484
OpcodeStr#_.Suffix#
24852485
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
@@ -2497,37 +2497,37 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
24972497
X86FoldableSchedWrite sched, X86VectorVTInfo _,
24982498
string mem, list<Register> _Uses = [MXCSR]>{
24992499
let ExeDomain = _.ExeDomain, Uses = _Uses in {
2500-
def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2500+
def ri : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
25012501
(ins _.RC:$src1, i32u8imm:$src2),
25022502
OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
25032503
[(set _.KRC:$dst,(X86Vfpclass (_.VT _.RC:$src1),
25042504
(i32 timm:$src2)))]>,
25052505
Sched<[sched]>;
2506-
def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
2506+
def rik : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
25072507
(ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
25082508
OpcodeStr#_.Suffix#
25092509
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
25102510
[(set _.KRC:$dst,(and _.KRCWM:$mask,
25112511
(X86Vfpclass_su (_.VT _.RC:$src1),
25122512
(i32 timm:$src2))))]>,
25132513
EVEX_K, Sched<[sched]>;
2514-
def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2514+
def mi : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
25152515
(ins _.MemOp:$src1, i32u8imm:$src2),
25162516
OpcodeStr#_.Suffix#"{"#mem#"}"#
25172517
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
25182518
[(set _.KRC:$dst,(X86Vfpclass
25192519
(_.VT (_.LdFrag addr:$src1)),
25202520
(i32 timm:$src2)))]>,
25212521
Sched<[sched.Folded, sched.ReadAfterFold]>;
2522-
def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2522+
def mik : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
25232523
(ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
25242524
OpcodeStr#_.Suffix#"{"#mem#"}"#
25252525
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
25262526
[(set _.KRC:$dst, (and _.KRCWM:$mask, (X86Vfpclass_su
25272527
(_.VT (_.LdFrag addr:$src1)),
25282528
(i32 timm:$src2))))]>,
25292529
EVEX_K, Sched<[sched.Folded, sched.ReadAfterFold]>;
2530-
def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2530+
def mbi : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
25312531
(ins _.ScalarMemOp:$src1, i32u8imm:$src2),
25322532
OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
25332533
_.BroadcastStr#", $dst|$dst, ${src1}"
@@ -2536,7 +2536,7 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
25362536
(_.VT (_.BroadcastLdFrag addr:$src1)),
25372537
(i32 timm:$src2)))]>,
25382538
EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
2539-
def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
2539+
def mbik : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
25402540
(ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
25412541
OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
25422542
_.BroadcastStr#", $dst {${mask}}|$dst {${mask}}, ${src1}"#
@@ -2551,21 +2551,21 @@ multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr,
25512551
// the memory form.
25522552
def : InstAlias<OpcodeStr#_.Suffix#mem#
25532553
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2554-
(!cast<Instruction>(NAME#"rr")
2554+
(!cast<Instruction>(NAME#"ri")
25552555
_.KRC:$dst, _.RC:$src1, i32u8imm:$src2), 0, "att">;
25562556
def : InstAlias<OpcodeStr#_.Suffix#mem#
25572557
"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2558-
(!cast<Instruction>(NAME#"rrk")
2558+
(!cast<Instruction>(NAME#"rik")
25592559
_.KRC:$dst, _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2), 0, "att">;
25602560
def : InstAlias<OpcodeStr#_.Suffix#mem#
25612561
"\t{$src2, ${src1}"#_.BroadcastStr#", $dst|$dst, ${src1}"#
25622562
_.BroadcastStr#", $src2}",
2563-
(!cast<Instruction>(NAME#"rmb")
2563+
(!cast<Instruction>(NAME#"mbi")
25642564
_.KRC:$dst, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">;
25652565
def : InstAlias<OpcodeStr#_.Suffix#mem#
25662566
"\t{$src2, ${src1}"#_.BroadcastStr#", $dst {${mask}}|"
25672567
"$dst {${mask}}, ${src1}"#_.BroadcastStr#", $src2}",
2568-
(!cast<Instruction>(NAME#"rmbk")
2568+
(!cast<Instruction>(NAME#"mbik")
25692569
_.KRC:$dst, _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">;
25702570
}
25712571

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7797,8 +7797,8 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
77977797
case X86::VFIXUPIMMSSZrri:
77987798
case X86::VFIXUPIMMSSZrrik:
77997799
case X86::VFIXUPIMMSSZrrikz:
7800-
case X86::VFPCLASSSSZrr:
7801-
case X86::VFPCLASSSSZrrk:
7800+
case X86::VFPCLASSSSZri:
7801+
case X86::VFPCLASSSSZrik:
78027802
case X86::VGETEXPSSZr:
78037803
case X86::VGETEXPSSZrk:
78047804
case X86::VGETEXPSSZrkz:
@@ -7966,8 +7966,8 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
79667966
case X86::VFIXUPIMMSDZrri:
79677967
case X86::VFIXUPIMMSDZrrik:
79687968
case X86::VFIXUPIMMSDZrrikz:
7969-
case X86::VFPCLASSSDZrr:
7970-
case X86::VFPCLASSSDZrrk:
7969+
case X86::VFPCLASSSDZri:
7970+
case X86::VFPCLASSSDZrik:
79717971
case X86::VGETEXPSDZr:
79727972
case X86::VGETEXPSDZrk:
79737973
case X86::VGETEXPSDZrkz:

‎llvm/lib/Target/X86/X86SchedIceLake.td‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -861,8 +861,8 @@ def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)kk",
861861
"VCMPPD(Z|Z128|Z256)rri",
862862
"VCMPPS(Z|Z128|Z256)rri",
863863
"VCMP(SD|SS)Zrr",
864-
"VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
865-
"VFPCLASS(SD|SS)Zrr",
864+
"VFPCLASS(PD|PS)(Z|Z128|Z256)ri",
865+
"VFPCLASS(SD|SS)Zri",
866866
"VPCMPB(Z|Z128|Z256)rri",
867867
"VPCMPD(Z|Z128|Z256)rri",
868868
"VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
@@ -1705,8 +1705,8 @@ def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm,
17051705
VPMOVSXWDYrm,
17061706
VPMOVZXWDYrm)>;
17071707
def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1708-
"VFPCLASSSDZrm(b?)",
1709-
"VFPCLASSSSZrm(b?)",
1708+
"VFPCLASSSDZm(b?)i",
1709+
"VFPCLASSSSZm(b?)i",
17101710
"(V?)PCMPGTQrm",
17111711
"VPERMI2DZ128rm(b?)",
17121712
"VPERMI2PDZ128rm(b?)",
@@ -1728,8 +1728,8 @@ def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
17281728
}
17291729
def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
17301730
"VCMP(SD|SS)Zrm",
1731-
"VFPCLASSPDZ128rm(b?)",
1732-
"VFPCLASSPSZ128rm(b?)",
1731+
"VFPCLASSPDZ128m(b?)i",
1732+
"VFPCLASSPSZ128m(b?)i",
17331733
"VPCMPBZ128rm(b?)i",
17341734
"VPCMPDZ128rm(b?)i",
17351735
"VPCMPEQ(B|D|Q|W)Z128rm(b?)",
@@ -1793,8 +1793,8 @@ def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> {
17931793
}
17941794
def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
17951795
"VCMPPS(Z|Z256)rm(b?)i",
1796-
"VFPCLASSPD(Z|Z256)rm(b?)",
1797-
"VFPCLASSPS(Z|Z256)rm(b?)",
1796+
"VFPCLASSPD(Z|Z256)m(b?)i",
1797+
"VFPCLASSPS(Z|Z256)m(b?)i",
17981798
"VPCMPB(Z|Z256)rm(b?)i",
17991799
"VPCMPD(Z|Z256)rm(b?)i",
18001800
"VPCMPEQB(Z|Z256)rm(b?)",

‎llvm/lib/Target/X86/X86SchedSapphireRapids.td‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -632,14 +632,14 @@ def : InstRW<[SPRWriteResGroup10], (instregex "^ADD_F(32|64)m$",
632632
"^VPOPCNT(D|Q)Z128rmbk(z?)$")>;
633633
def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
634634
"^(V?)PCMPGTQrm$",
635-
"^VFPCLASSP(D|H|S)Z128rmb$",
635+
"^VFPCLASSP(D|H|S)Z128mbi$",
636636
"^VPACK(S|U)S(DW|WB)Z128rm$",
637637
"^VPACK(S|U)SDWZ128rmb$",
638638
"^VPM(AX|IN)(S|U)QZ128rm((b|k|bk|kz)?)$",
639639
"^VPM(AX|IN)(S|U)QZ128rmbkz$",
640640
"^VPMULTISHIFTQBZ128rm(b?)$")>;
641-
def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instrs VFPCLASSPHZ128rm)>;
642-
def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)rm$",
641+
def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instrs VFPCLASSPHZ128mi)>;
642+
def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)mi$",
643643
"^VPERM(I|T)2(D|Q|PS)Z128rm((b|k|bk|kz)?)$",
644644
"^VPERM(I|T)2(D|Q|PS)Z128rmbkz$",
645645
"^VPERM(I|T)2PDZ128rm((b|k|bk|kz)?)$",
@@ -670,8 +670,8 @@ def : InstRW<[SPRWriteResGroup12], (instregex "^ADD_F(P?)rST0$",
670670
"^VCMPP(D|H|S)Z(128|256)rri(k?)$",
671671
"^VCMPS(D|H|S)Zrri$",
672672
"^VCMPS(D|H|S)Zrr(b?)i_Int(k?)$",
673-
"^VFPCLASSP(D|H|S)Z(128|256)rr(k?)$",
674-
"^VFPCLASSS(D|H|S)Zrr(k?)$",
673+
"^VFPCLASSP(D|H|S)Z(128|256)ri(k?)$",
674+
"^VFPCLASSS(D|H|S)Zri(k?)$",
675675
"^VPACK(S|U)S(DW|WB)Yrr$",
676676
"^VPACK(S|U)S(DW|WB)Z(128|256)rr$",
677677
"^VPALIGNRZ(128|256)rrik(z?)$",
@@ -1697,8 +1697,8 @@ def : InstRW<[SPRWriteResGroup134], (instregex "^VPBROADCAST(BY|WZ)rm$",
16971697
"^VPBROADCAST(B|W)Z256rm$",
16981698
"^VPBROADCAST(BZ|WY)rm$")>;
16991699
def : InstRW<[SPRWriteResGroup134, ReadAfterLd], (instrs MMX_PINSRWrmi)>;
1700-
def : InstRW<[SPRWriteResGroup134, ReadAfterVecXLd], (instregex "^VFPCLASSP(D|S)Z128rm$")>;
1701-
def : InstRW<[SPRWriteResGroup134, ReadAfterVecLd], (instregex "^VFPCLASSS(D|H|S)Zrm$")>;
1700+
def : InstRW<[SPRWriteResGroup134, ReadAfterVecXLd], (instregex "^VFPCLASSP(D|S)Z128mi$")>;
1701+
def : InstRW<[SPRWriteResGroup134, ReadAfterVecLd], (instregex "^VFPCLASSS(D|H|S)Zmi$")>;
17021702
def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instregex "^VPALIGNR(Y|Z256)rmi$")>;
17031703
def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instrs VPSHUFBZrm)>;
17041704

@@ -2659,7 +2659,7 @@ def : InstRW<[SPRWriteResGroup258], (instregex "^VPBROADCAST(B|W)Z128rmk(z?)$",
26592659
def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((256)?)rm(bi|ik)$",
26602660
"^VALIGN(D|Q)Z((256)?)rmbik(z?)$",
26612661
"^VALIGN(D|Q)Z((256)?)rmi((kz)?)$",
2662-
"^VFPCLASSP(D|H|S)Z((256)?)rmb$",
2662+
"^VFPCLASSP(D|H|S)Z((256)?)mbi$",
26632663
"^VPACK(S|U)S(DW|WB)(Y|Z)rm$",
26642664
"^VPACK(S|U)S(DW|WB)Z256rm$",
26652665
"^VPACK(S|U)SDWZ((256)?)rmb$",
@@ -2724,7 +2724,7 @@ def SPRWriteResGroup263 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
27242724
}
27252725
def : InstRW<[SPRWriteResGroup263, ReadAfterVecXLd], (instregex "^VCMPP(D|H|S)Z128rm(bi|ik)$",
27262726
"^VCMPP(D|H|S)Z128rm(i|bik)$",
2727-
"^VFPCLASSP(D|H|S)Z128rm(b?)k$",
2727+
"^VFPCLASSP(D|H|S)Z128m(b?)ik$",
27282728
"^VPCMP(B|D|Q|W|UD|UQ|UW)Z128rmi(k?)$",
27292729
"^VPCMP(D|Q|UQ)Z128rmbi(k?)$",
27302730
"^VPCMP(EQ|GT)(B|D|Q|W)Z128rm(k?)$",
@@ -2735,7 +2735,7 @@ def : InstRW<[SPRWriteResGroup263, ReadAfterVecXLd], (instregex "^VCMPP(D|H|S)Z1
27352735
"^VPTEST(N?)M(D|Q)Z128rmb(k?)$")>;
27362736
def : InstRW<[SPRWriteResGroup263, ReadAfterVecYLd], (instregex "^VCMPP(D|H|S)Z((256)?)rm(bi|ik)$",
27372737
"^VCMPP(D|H|S)Z((256)?)rm(i|bik)$",
2738-
"^VFPCLASSP(D|H|S)Z((256)?)rm(b?)k$",
2738+
"^VFPCLASSP(D|H|S)Z((256)?)m(b?)ik$",
27392739
"^VPCMP(B|D|Q|W|UD|UQ|UW)Z((256)?)rmi(k?)$",
27402740
"^VPCMP(D|Q|UQ)Z((256)?)rmbi(k?)$",
27412741
"^VPCMP(EQ|GT)(B|D|Q|W)Z((256)?)rm(k?)$",
@@ -2746,7 +2746,7 @@ def : InstRW<[SPRWriteResGroup263, ReadAfterVecYLd], (instregex "^VCMPP(D|H|S)Z(
27462746
"^VPTEST(N?)M(D|Q)Z((256)?)rmb(k?)$")>;
27472747
def : InstRW<[SPRWriteResGroup263, ReadAfterVecLd], (instregex "^VCMPS(D|H|S)Zrmi$",
27482748
"^VCMPS(D|H|S)Zrmi_Int(k?)$",
2749-
"^VFPCLASSS(D|H|S)Zrmk$")>;
2749+
"^VFPCLASSS(D|H|S)Zmik$")>;
27502750

27512751
def SPRWriteResGroup264 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
27522752
let Latency = 10;

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