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Add tests for G_UADDO, G_UADDE
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6 files changed

+531
-46
lines changed

6 files changed

+531
-46
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -471,16 +471,20 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
471471
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
472472
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}})
473473
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
474-
// Split 64-bit add/sub into two 32-bit ops on VGPRs
475-
.Uni(S64, {{Vgpr64}, {Vgpr64, Vgpr64}, SplitTo32})
476-
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}, SplitTo32})
477474
.Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}})
478-
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
475+
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
476+
// Split 64-bit add/sub into two 32-bit ops on VGPRs
477+
.Uni(S64, {{Sgpr64}, {Sgpr64, Sgpr64}, SplitTo32})
478+
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr64}, SplitTo32});
479479

480-
addRulesForGOpcs({G_UADDO, G_USUBO, G_UADDE, G_USUBE}, Standard)
481-
.Uni(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32}})
480+
addRulesForGOpcs({G_UADDO, G_USUBO}, Standard)
481+
.Uni(S32, {{Sgpr32, Sgpr32}, {Sgpr32, Sgpr32}})
482482
.Div(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32}});
483483

484+
addRulesForGOpcs({G_UADDE, G_USUBE}, Standard)
485+
.Uni(S32, {{Sgpr32, Sgpr32}, {Sgpr32, Sgpr32, Sgpr32}})
486+
.Div(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32, Vcc}});
487+
484488
addRulesForGOpcs({G_MUL}, Standard).Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}});
485489

486490
addRulesForGOpcs({G_XOR, G_OR, G_AND}, StandardB)

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,7 @@ enum RegBankLLTMappingApplyID {
127127
None,
128128
IntrId,
129129
Imm,
130+
Scc,
130131
Vcc,
131132

132133
// sgpr scalars, pointers, vectors and B-types

‎llvm/test/CodeGen/AMDGPU/GlobalISel/add.ll‎

Lines changed: 192 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,192 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefix=GFX7 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
5+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
6+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s
7+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12 %s
8+
9+
define i16 @s_add_i16(i16 %a, i16 %b) {
10+
; GFX7-LABEL: s_add_i16:
11+
; GFX7: ; %bb.0:
12+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
13+
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
14+
; GFX7-NEXT: s_setpc_b64 s[30:31]
15+
;
16+
; GFX9-LABEL: s_add_i16:
17+
; GFX9: ; %bb.0:
18+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19+
; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
20+
; GFX9-NEXT: s_setpc_b64 s[30:31]
21+
;
22+
; GFX8-LABEL: s_add_i16:
23+
; GFX8: ; %bb.0:
24+
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
25+
; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
26+
; GFX8-NEXT: s_setpc_b64 s[30:31]
27+
;
28+
; GFX10-LABEL: s_add_i16:
29+
; GFX10: ; %bb.0:
30+
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
31+
; GFX10-NEXT: v_add_nc_u16 v0, v0, v1
32+
; GFX10-NEXT: s_setpc_b64 s[30:31]
33+
;
34+
; GFX11-LABEL: s_add_i16:
35+
; GFX11: ; %bb.0:
36+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
37+
; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l
38+
; GFX11-NEXT: s_setpc_b64 s[30:31]
39+
;
40+
; GFX12-LABEL: s_add_i16:
41+
; GFX12: ; %bb.0:
42+
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
43+
; GFX12-NEXT: s_wait_expcnt 0x0
44+
; GFX12-NEXT: s_wait_samplecnt 0x0
45+
; GFX12-NEXT: s_wait_bvhcnt 0x0
46+
; GFX12-NEXT: s_wait_kmcnt 0x0
47+
; GFX12-NEXT: v_add_nc_u16 v0, v0, v1
48+
; GFX12-NEXT: s_setpc_b64 s[30:31]
49+
%c = add i16 %a, %b
50+
ret i16 %c
51+
}
52+
53+
define i32 @s_add_i32(i32 %a, i32 %b) {
54+
; GFX7-LABEL: s_add_i32:
55+
; GFX7: ; %bb.0:
56+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
57+
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1
58+
; GFX7-NEXT: s_setpc_b64 s[30:31]
59+
;
60+
; GFX9-LABEL: s_add_i32:
61+
; GFX9: ; %bb.0:
62+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
63+
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
64+
; GFX9-NEXT: s_setpc_b64 s[30:31]
65+
;
66+
; GFX8-LABEL: s_add_i32:
67+
; GFX8: ; %bb.0:
68+
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69+
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
70+
; GFX8-NEXT: s_setpc_b64 s[30:31]
71+
;
72+
; GFX10-LABEL: s_add_i32:
73+
; GFX10: ; %bb.0:
74+
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
75+
; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
76+
; GFX10-NEXT: s_setpc_b64 s[30:31]
77+
;
78+
; GFX11-LABEL: s_add_i32:
79+
; GFX11: ; %bb.0:
80+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
81+
; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1
82+
; GFX11-NEXT: s_setpc_b64 s[30:31]
83+
;
84+
; GFX12-LABEL: s_add_i32:
85+
; GFX12: ; %bb.0:
86+
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
87+
; GFX12-NEXT: s_wait_expcnt 0x0
88+
; GFX12-NEXT: s_wait_samplecnt 0x0
89+
; GFX12-NEXT: s_wait_bvhcnt 0x0
90+
; GFX12-NEXT: s_wait_kmcnt 0x0
91+
; GFX12-NEXT: v_add_nc_u32_e32 v0, v0, v1
92+
; GFX12-NEXT: s_setpc_b64 s[30:31]
93+
%c = add i32 %a, %b
94+
ret i32 %c
95+
}
96+
97+
define <2 x i16> @s_add_v2i16(<2 x i16> %a, <2 x i16> %b) {
98+
; GFX7-LABEL: s_add_v2i16:
99+
; GFX7: ; %bb.0:
100+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
101+
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
102+
; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v3
103+
; GFX7-NEXT: s_setpc_b64 s[30:31]
104+
;
105+
; GFX9-LABEL: s_add_v2i16:
106+
; GFX9: ; %bb.0:
107+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
108+
; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
109+
; GFX9-NEXT: s_setpc_b64 s[30:31]
110+
;
111+
; GFX8-LABEL: s_add_v2i16:
112+
; GFX8: ; %bb.0:
113+
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
114+
; GFX8-NEXT: v_add_u16_e32 v2, v0, v1
115+
; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
116+
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
117+
; GFX8-NEXT: s_setpc_b64 s[30:31]
118+
;
119+
; GFX10-LABEL: s_add_v2i16:
120+
; GFX10: ; %bb.0:
121+
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
122+
; GFX10-NEXT: v_pk_add_u16 v0, v0, v1
123+
; GFX10-NEXT: s_setpc_b64 s[30:31]
124+
;
125+
; GFX11-LABEL: s_add_v2i16:
126+
; GFX11: ; %bb.0:
127+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
128+
; GFX11-NEXT: v_pk_add_u16 v0, v0, v1
129+
; GFX11-NEXT: s_setpc_b64 s[30:31]
130+
;
131+
; GFX12-LABEL: s_add_v2i16:
132+
; GFX12: ; %bb.0:
133+
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
134+
; GFX12-NEXT: s_wait_expcnt 0x0
135+
; GFX12-NEXT: s_wait_samplecnt 0x0
136+
; GFX12-NEXT: s_wait_bvhcnt 0x0
137+
; GFX12-NEXT: s_wait_kmcnt 0x0
138+
; GFX12-NEXT: v_pk_add_u16 v0, v0, v1
139+
; GFX12-NEXT: s_setpc_b64 s[30:31]
140+
%c = add <2 x i16> %a, %b
141+
ret <2 x i16> %c
142+
}
143+
144+
define i64 @s_add_i64(i64 %a, i64 %b) {
145+
; GFX7-LABEL: s_add_i64:
146+
; GFX7: ; %bb.0:
147+
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
148+
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
149+
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
150+
; GFX7-NEXT: s_setpc_b64 s[30:31]
151+
;
152+
; GFX9-LABEL: s_add_i64:
153+
; GFX9: ; %bb.0:
154+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
155+
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
156+
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
157+
; GFX9-NEXT: s_setpc_b64 s[30:31]
158+
;
159+
; GFX8-LABEL: s_add_i64:
160+
; GFX8: ; %bb.0:
161+
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
162+
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
163+
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
164+
; GFX8-NEXT: s_setpc_b64 s[30:31]
165+
;
166+
; GFX10-LABEL: s_add_i64:
167+
; GFX10: ; %bb.0:
168+
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
169+
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
170+
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
171+
; GFX10-NEXT: s_setpc_b64 s[30:31]
172+
;
173+
; GFX11-LABEL: s_add_i64:
174+
; GFX11: ; %bb.0:
175+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
176+
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
177+
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
178+
; GFX11-NEXT: s_setpc_b64 s[30:31]
179+
;
180+
; GFX12-LABEL: s_add_i64:
181+
; GFX12: ; %bb.0:
182+
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
183+
; GFX12-NEXT: s_wait_expcnt 0x0
184+
; GFX12-NEXT: s_wait_samplecnt 0x0
185+
; GFX12-NEXT: s_wait_bvhcnt 0x0
186+
; GFX12-NEXT: s_wait_kmcnt 0x0
187+
; GFX12-NEXT: v_add_nc_u32_e32 v0, v0, v2
188+
; GFX12-NEXT: v_add_nc_u32_e32 v1, v1, v3
189+
; GFX12-NEXT: s_setpc_b64 s[30:31]
190+
%c = add i64 %a, %b
191+
ret i64 %c
192+
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,62 @@ body: |
7575
%2:_(s32) = G_ADD %0, %1
7676
...
7777

78+
---
79+
name: uaddo_s32_ss
80+
legalized: true
81+
82+
body: |
83+
bb.0:
84+
liveins: $sgpr0, $sgpr1
85+
; CHECK-LABEL: name: uaddo_s32_ss
86+
; CHECK: liveins: $sgpr0, $sgpr1
87+
; CHECK-NEXT: {{ $}}
88+
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
89+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
90+
; CHECK-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s1) = G_UADDO [[COPY]], [[COPY1]]
91+
%0:_(s32) = COPY $sgpr0
92+
%1:_(s32) = COPY $sgpr1
93+
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
94+
...
95+
96+
---
97+
name: uaddo_s32_sv
98+
legalized: true
99+
100+
body: |
101+
bb.0:
102+
liveins: $sgpr0, $vgpr1
103+
; CHECK-LABEL: name: uaddo_s32_sv
104+
; CHECK: liveins: $sgpr0, $vgpr1
105+
; CHECK-NEXT: {{ $}}
106+
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
107+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
108+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
109+
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY2]], [[COPY1]]
110+
%0:_(s32) = COPY $sgpr0
111+
%1:_(s32) = COPY $vgpr1
112+
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
113+
...
114+
115+
---
116+
name: uaddo_s32_vs
117+
legalized: true
118+
119+
body: |
120+
bb.0:
121+
liveins: $vgpr0, $sgpr1
122+
; CHECK-LABEL: name: uaddo_s32_vs
123+
; CHECK: liveins: $vgpr0, $sgpr1
124+
; CHECK-NEXT: {{ $}}
125+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
126+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
127+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
128+
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY]], [[COPY2]]
129+
%0:_(s32) = COPY $vgpr0
130+
%1:_(s32) = COPY $sgpr1
131+
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
132+
...
133+
78134
---
79135
name: uaddo_s32_vv
80136
legalized: true
@@ -93,6 +149,74 @@ body: |
93149
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
94150
...
95151

152+
---
153+
name: uadde_s32_ss
154+
legalized: true
155+
156+
body: |
157+
bb.0:
158+
liveins: $sgpr0, $sgpr1, $sgpr2
159+
; CHECK-LABEL: name: uadde_s32_ss
160+
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
161+
; CHECK-NEXT: {{ $}}
162+
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
163+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
164+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
165+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32)
166+
; CHECK-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]
167+
%0:_(s32) = COPY $sgpr0
168+
%1:_(s32) = COPY $sgpr1
169+
%2:_(s32) = COPY $sgpr2
170+
%3:_(s1) = G_TRUNC %2
171+
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
172+
...
173+
174+
---
175+
name: uadde_s32_sv
176+
legalized: true
177+
178+
body: |
179+
bb.0:
180+
liveins: $sgpr0, $vgpr1, $sgpr2
181+
; CHECK-LABEL: name: uadde_s32_sv
182+
; CHECK: liveins: $sgpr0, $vgpr1, $sgpr2
183+
; CHECK-NEXT: {{ $}}
184+
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
185+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
186+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
187+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
188+
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32)
189+
; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY1]], [[AMDGPU_COPY_VCC_SCC]]
190+
%0:_(s32) = COPY $sgpr0
191+
%1:_(s32) = COPY $vgpr1
192+
%2:_(s32) = COPY $sgpr2
193+
%3:_(s1) = G_TRUNC %2
194+
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
195+
...
196+
197+
---
198+
name: uadde_s32_vs
199+
legalized: true
200+
201+
body: |
202+
bb.0:
203+
liveins: $vgpr0, $sgpr1, $sgpr2
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; CHECK-LABEL: name: uadde_s32_vs
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; CHECK: liveins: $vgpr0, $sgpr1, $sgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32)
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; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[AMDGPU_COPY_VCC_SCC]]
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s1) = G_TRUNC %2
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%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
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...
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96220
---
97221
name: uadde_s32_vv
98222
legalized: true

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