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[VPlan] Extend replicates in isUniformAcrossVFsAndUFs
The check for a load or store is unnecessary.
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4 files changed

+27
-32
lines changed

4 files changed

+27
-32
lines changed

‎llvm/lib/Transforms/Vectorize/VPlanUtils.cpp‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -110,12 +110,7 @@ bool vputils::isUniformAcrossVFsAndUFs(VPValue *V) {
110110
return TypeSwitch<const VPRecipeBase *, bool>(R)
111111
.Case<VPDerivedIVRecipe>([](const auto *R) { return true; })
112112
.Case<VPReplicateRecipe>([](const auto *R) {
113-
// Loads and stores that are uniform across VF lanes are handled by
114-
// VPReplicateRecipe.IsUniform. They are also uniform across UF parts if
115-
// all their operands are invariant.
116-
// TODO: Further relax the restrictions.
117113
return R->isSingleScalar() &&
118-
(isa<LoadInst, StoreInst>(R->getUnderlyingValue())) &&
119114
all_of(R->operands(), isUniformAcrossVFsAndUFs);
120115
})
121116
.Case<VPInstruction>([](const auto *VPI) {

‎llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll‎

Lines changed: 19 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -66,8 +66,9 @@ define void @replicating_load_used_as_store_addr_2(ptr noalias %invar.dst, ptr n
6666
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
6767
; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
6868
; CHECK: [[MIDDLE_BLOCK]]:
69-
; CHECK-NEXT: br [[EXIT:label %.*]]
70-
; CHECK: [[SCALAR_PH:.*:]]
69+
; CHECK-NEXT: br label %[[EXIT:.*]]
70+
; CHECK: [[EXIT]]:
71+
; CHECK-NEXT: ret void
7172
;
7273
entry:
7374
br label %loop
@@ -107,15 +108,15 @@ define void @replicating_load_used_as_store_addr_3(ptr noalias %src, ptr noalias
107108
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
108109
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP6]]
109110
; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
110-
; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
111111
; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP5]] to i8
112112
; CHECK-NEXT: store i8 [[TMP8]], ptr [[INVAR_DST]], align 1
113113
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
114114
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
115115
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
116116
; CHECK: [[MIDDLE_BLOCK]]:
117-
; CHECK-NEXT: br [[EXIT:label %.*]]
118-
; CHECK: [[SCALAR_PH:.*:]]
117+
; CHECK-NEXT: br label %[[EXIT:.*]]
118+
; CHECK: [[EXIT]]:
119+
; CHECK-NEXT: ret void
119120
;
120121
entry:
121122
br label %loop
@@ -463,21 +464,21 @@ define void @test_prefer_vector_addressing(ptr %start, ptr %ms, ptr noalias %src
463464
; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP11]]
464465
; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP12]]
465466
; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP13]]
466-
; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[NEXT_GEP]], align 1, !tbaa [[LONG_LONG_TBAA14:![0-9]+]]
467-
; CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[NEXT_GEP3]], align 1, !tbaa [[LONG_LONG_TBAA14]]
468-
; CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[NEXT_GEP4]], align 1, !tbaa [[LONG_LONG_TBAA14]]
469-
; CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[NEXT_GEP5]], align 1, !tbaa [[LONG_LONG_TBAA14]]
467+
; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[NEXT_GEP]], align 1, !tbaa [[LONG_LONG_TBAA12:![0-9]+]]
468+
; CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[NEXT_GEP3]], align 1, !tbaa [[LONG_LONG_TBAA12]]
469+
; CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[NEXT_GEP4]], align 1, !tbaa [[LONG_LONG_TBAA12]]
470+
; CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[NEXT_GEP5]], align 1, !tbaa [[LONG_LONG_TBAA12]]
470471
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP14]]
471472
; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP15]]
472473
; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP16]]
473474
; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP17]]
474-
; CHECK-NEXT: store i32 0, ptr [[TMP18]], align 4, !tbaa [[INT_TBAA19:![0-9]+]]
475-
; CHECK-NEXT: store i32 0, ptr [[TMP19]], align 4, !tbaa [[INT_TBAA19]]
476-
; CHECK-NEXT: store i32 0, ptr [[TMP20]], align 4, !tbaa [[INT_TBAA19]]
477-
; CHECK-NEXT: store i32 0, ptr [[TMP21]], align 4, !tbaa [[INT_TBAA19]]
475+
; CHECK-NEXT: store i32 0, ptr [[TMP18]], align 4, !tbaa [[INT_TBAA17:![0-9]+]]
476+
; CHECK-NEXT: store i32 0, ptr [[TMP19]], align 4, !tbaa [[INT_TBAA17]]
477+
; CHECK-NEXT: store i32 0, ptr [[TMP20]], align 4, !tbaa [[INT_TBAA17]]
478+
; CHECK-NEXT: store i32 0, ptr [[TMP21]], align 4, !tbaa [[INT_TBAA17]]
478479
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
479480
; CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
480-
; CHECK-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
481+
; CHECK-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
481482
; CHECK: [[MIDDLE_BLOCK]]:
482483
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP6]], [[N_VEC]]
483484
; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
@@ -578,10 +579,11 @@ define double @test_scalarization_cost_for_load_of_address(ptr %src.0, ptr %src.
578579
; CHECK-NEXT: [[TMP20:%.*]] = fmul <2 x double> [[TMP9]], [[TMP19]]
579580
; CHECK-NEXT: [[TMP21]] = call double @llvm.vector.reduce.fadd.v2f64(double [[VEC_PHI]], <2 x double> [[TMP20]])
580581
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
581-
; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
582+
; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
582583
; CHECK: [[MIDDLE_BLOCK]]:
583-
; CHECK-NEXT: br [[EXIT:label %.*]]
584-
; CHECK: [[SCALAR_PH:.*:]]
584+
; CHECK-NEXT: br label %[[EXIT:.*]]
585+
; CHECK: [[EXIT]]:
586+
; CHECK-NEXT: ret double [[TMP21]]
585587
;
586588
entry:
587589
br label %loop

‎llvm/test/Transforms/LoopVectorize/assume.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,9 @@ define void @test1(ptr noalias nocapture %a, ptr noalias nocapture readonly %b)
3434
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1600
3535
; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
3636
; CHECK: [[MIDDLE_BLOCK]]:
37-
; CHECK-NEXT: br [[FOR_END:label %.*]]
38-
; CHECK: [[SCALAR_PH:.*:]]
37+
; CHECK-NEXT: br label %[[FOR_END:.*]]
38+
; CHECK: [[FOR_END]]:
39+
; CHECK-NEXT: ret void
3940
;
4041
entry:
4142
br label %for.body
@@ -77,25 +78,24 @@ define void @test2(ptr noalias %a, ptr noalias %b) {
7778
; CHECK: [[VECTOR_BODY]]:
7879
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
7980
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
80-
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
8181
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]
8282
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 2
8383
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x float>, ptr [[TMP3]], align 4
8484
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x float>, ptr [[TMP4]], align 4
8585
; CHECK-NEXT: [[TMP5:%.*]] = fadd <2 x float> [[WIDE_LOAD]], splat (float 1.000000e+00)
8686
; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x float> [[WIDE_LOAD1]], splat (float 1.000000e+00)
8787
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND4]])
88-
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND4]])
8988
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]
9089
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 2
9190
; CHECK-NEXT: store <2 x float> [[TMP5]], ptr [[TMP7]], align 4
9291
; CHECK-NEXT: store <2 x float> [[TMP6]], ptr [[TMP8]], align 4
9392
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
9493
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1600
95-
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
94+
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
9695
; CHECK: [[MIDDLE_BLOCK]]:
97-
; CHECK-NEXT: br [[FOR_END:label %.*]]
98-
; CHECK: [[SCALAR_PH:.*:]]
96+
; CHECK-NEXT: br label %[[FOR_END:.*]]
97+
; CHECK: [[FOR_END]]:
98+
; CHECK-NEXT: ret void
9999
;
100100
entry:
101101
%ptrint = ptrtoint ptr %a to i64
@@ -163,7 +163,7 @@ define void @predicated_assume(ptr noalias nocapture readonly %a, ptr noalias no
163163
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
164164
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[STEP_ADD]], splat (i64 2)
165165
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
166-
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
166+
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
167167
; CHECK: [[MIDDLE_BLOCK]]:
168168
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
169169
; CHECK-NEXT: br i1 [[CMP_N]], [[FOR_COND_CLEANUP_LOOPEXIT:label %.*]], label %[[SCALAR_PH]]

‎llvm/test/Transforms/LoopVectorize/scalable-assume.ll‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,6 @@ define void @test2(ptr %a, ptr noalias %b) {
9292
; CHECK: [[VECTOR_BODY]]:
9393
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
9494
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
95-
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
9695
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]
9796
; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
9897
; CHECK-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP11]], 1
@@ -102,7 +101,6 @@ define void @test2(ptr %a, ptr noalias %b) {
102101
; CHECK-NEXT: [[TMP14:%.*]] = fadd <vscale x 2 x float> [[WIDE_LOAD]], splat (float 1.000000e+00)
103102
; CHECK-NEXT: [[TMP15:%.*]] = fadd <vscale x 2 x float> [[WIDE_LOAD3]], splat (float 1.000000e+00)
104103
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND4]])
105-
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND4]])
106104
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[INDEX]]
107105
; CHECK-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64()
108106
; CHECK-NEXT: [[TMP18:%.*]] = shl nuw i64 [[TMP17]], 1

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