Responding to review comments

- minor cleanup
- allow optimizing concat_vectors(sqdmulh,sqdmulh) -> sqdmulh
- testing EVTs better

Change-Id: I0404fb9900896050baac372b7f7ce3a5b03517b9

Author: nasherm

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -2392,6 +2392,15 @@ static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
   return false;
 }
 
+bool isVectorizedBinOp(unsigned Opcode) {
+  switch (Opcode) {
+  case AArch64ISD::SQDMULH:
+    return true;
+  default:
+    return false;
+  }
+}
+
 // isOpcWithIntImmediate - This method tests to see if the node is a specific
 // opcode and that it has a immediate integer right operand.
 // If so Imm will receive the value.
@@ -20126,8 +20135,9 @@ static SDValue performConcatVectorsCombine(SDNode *N,
   // size, combine into an binop of two contacts of the source vectors. eg:
   // concat(uhadd(a,b), uhadd(c, d)) -> uhadd(concat(a, c), concat(b, d))
   if (N->getNumOperands() == 2 && N0Opc == N1Opc && VT.is128BitVector() &&
-      DAG.getTargetLoweringInfo().isBinOp(N0Opc) && N0->hasOneUse() &&
-      N1->hasOneUse()) {
+      (DAG.getTargetLoweringInfo().isBinOp(N0Opc) ||
+       isVectorizedBinOp(N0Opc)) &&
+      N0->hasOneUse() && N1->hasOneUse()) {
     SDValue N00 = N0->getOperand(0);
     SDValue N01 = N0->getOperand(1);
     SDValue N10 = N1->getOperand(0);
@@ -20986,7 +20996,7 @@ static SDValue performBuildVectorCombine(SDNode *N,
   return SDValue();
 }
 
-// A special combine for the vqdmulh family of instructions.
+// A special combine for the sqdmulh family of instructions.
 // smin( sra ( mul( sext v0, sext v1 ) ), SHIFT_AMOUNT ),
 // SATURATING_VAL ) can be reduced to sext(sqdmulh(...))
 static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
@@ -21043,24 +21053,20 @@ static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
   SDValue SExt0 = Mul.getOperand(0);
   SDValue SExt1 = Mul.getOperand(1);
 
-  if (SExt0.getOpcode() != ISD::SIGN_EXTEND ||
-      SExt1.getOpcode() != ISD::SIGN_EXTEND ||
-      SExt0.getValueType() != SExt1.getValueType())
-    return SDValue();
+  EVT SExt0Type = SExt0.getOperand(0).getValueType();
+  EVT SExt1Type = SExt1.getOperand(0).getValueType();
 
-  if ((ShiftAmt == 16 && (SExt0.getValueType() != MVT::v8i32 &&
-                          SExt0.getValueType() != MVT::v4i32)) ||
-      (ShiftAmt == 32 && (SExt0.getValueType() != MVT::v4i64 &&
-                          SExt0.getValueType() != MVT::v2i64)))
+  if (SExt0.getOpcode() != ISD::SIGN_EXTEND ||
+      SExt1.getOpcode() != ISD::SIGN_EXTEND || SExt0Type != SExt1Type ||
+      SExt0Type.getScalarType() != ScalarType ||
+      SExt0Type.getFixedSizeInBits() > 128)
     return SDValue();
 
   SDValue V0 = SExt0.getOperand(0);
   SDValue V1 = SExt1.getOperand(0);
 
   SDLoc DL(SMin);
-  EVT VecVT = N->getValueType(0);
-  SDValue SQDMULH = DAG.getNode(AArch64ISD::SQDMULH, DL, VecVT, V0, V1);
-  return DAG.getNode(ISD::SIGN_EXTEND, DL, N->getValueType(0), SQDMULH);
+  return DAG.getNode(AArch64ISD::SQDMULH, DL, SExt0Type, V0, V1);
 }
 
 static SDValue performTruncateCombine(SDNode *N, SelectionDAG &DAG,

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -9442,13 +9442,10 @@ def : Pat<(v4i32 (mulhu V128:$Rn, V128:$Rm)),
 
 def : Pat<(v4i16 (AArch64sqdmulh (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
           (SQDMULHv4i16 V64:$Rn, V64:$Rm)>;
-
 def : Pat<(v2i32 (AArch64sqdmulh (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
           (SQDMULHv2i32 V64:$Rn, V64:$Rm)>;
-
 def : Pat<(v8i16 (AArch64sqdmulh (v8i16 V128:$Rn), (v8i16 V128:$Rm))),
           (SQDMULHv8i16 V128:$Rn, V128:$Rm)>;
-
 def : Pat<(v4i32 (AArch64sqdmulh (v4i32 V128:$Rn), (v4i32 V128:$Rm))),
           (SQDMULHv4i32 V128:$Rn, V128:$Rm)>;
 

llvm/test/CodeGen/AArch64/saturating-vec-smull.ll

@@ -60,16 +60,8 @@ define <4 x i32> @saturating_4xi32(<4 x i32> %a, <4 x i32> %b) {
 define <8 x i32> @saturating_8xi32(<8 x i32> %a, <8 x i32> %b) {
 ; CHECK-LABEL: saturating_8xi32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v4.16b, v1.16b, v1.16b, #8
-; CHECK-NEXT:    ext v5.16b, v3.16b, v3.16b, #8
-; CHECK-NEXT:    ext v6.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    ext v7.16b, v2.16b, v2.16b, #8
-; CHECK-NEXT:    sqdmulh v1.2s, v3.2s, v1.2s
-; CHECK-NEXT:    sqdmulh v0.2s, v2.2s, v0.2s
-; CHECK-NEXT:    sqdmulh v4.2s, v5.2s, v4.2s
-; CHECK-NEXT:    sqdmulh v3.2s, v7.2s, v6.2s
-; CHECK-NEXT:    mov v1.d[1], v4.d[0]
-; CHECK-NEXT:    mov v0.d[1], v3.d[0]
+; CHECK-NEXT:    sqdmulh v1.4s, v3.4s, v1.4s
+; CHECK-NEXT:    sqdmulh v0.4s, v2.4s, v0.4s
 ; CHECK-NEXT:    ret
   %as = sext <8 x i32> %a to <8 x i64>
   %bs = sext <8 x i32> %b to <8 x i64>