- Changes relating to ConstraintInfo for setting flag output CC upper bound

anoopkg6 · anoopkg6 · commit 7ea0c5f7f62f · 2025-02-25T03:27:00.000+01:00
for all backend suuporting flag output operand (X86, AARCH64 and SystemZ).
- Remove all changes target specific changes from SelectionDAGBuiler.cpp.
- Added getJumpConditionMergingParams for SystemZ for setting cost for
  merging srl/ipm/cc.
- TODO: Handle the cases where simplifyBranchOnICmpChain creates switch table
  while folding branch on And'd or Or'd chain of icmp instructions.
diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h
@@ -1119,7 +1119,7 @@ class TargetInfo : public TransferrableTargetInfo,
   public:
     ConstraintInfo(StringRef ConstraintStr, StringRef Name)
         : Flags(0), TiedOperand(-1), ConstraintStr(ConstraintStr.str()),
-          Name(Name.str()), FlagOutputCCUpperBound(2) {
+          Name(Name.str()), FlagOutputCCUpperBound(0) {
       ImmRange.Min = ImmRange.Max = 0;
       ImmRange.isConstrained = false;
     }
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1552,6 +1552,7 @@ bool AArch64TargetInfo::validateAsmConstraint(
     if (const unsigned Len = matchAsmCCConstraint(Name)) {
       Name += Len - 1;
       Info.setAllowsRegister();
+      Info.setFlagOutputCCUpperBound(2);
       return true;
     }
   }
diff --git a/clang/lib/Basic/Targets/SystemZ.cpp b/clang/lib/Basic/Targets/SystemZ.cpp
@@ -100,7 +100,7 @@ bool SystemZTargetInfo::validateAsmConstraint(
     return true;
   case '@':
     // CC condition changes.
-    if (!StringRef("@cc").compare(Name)) {
+    if (StringRef(Name) == "@cc") {
       Name += 2;
       Info.setAllowsRegister();
       Info.setFlagOutputCCUpperBound(4);
diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h
@@ -120,10 +120,8 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo {
 
   std::string convertConstraint(const char *&Constraint) const override {
     if (llvm::StringRef(Constraint) == "@cc") {
-      auto Len = llvm::StringRef("@cc").size();
-      std::string Converted = std::string("{@cc}");
-      Constraint += Len - 1;
-      return Converted;
+      Constraint += 2;
+      return std::string("{@cc}");
     }
     switch (Constraint[0]) {
     case 'p': // Keep 'p' constraint.
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
@@ -1580,6 +1580,7 @@ bool X86TargetInfo::validateAsmConstraint(
     if (auto Len = matchAsmCCConstraint(Name)) {
       Name += Len - 1;
       Info.setAllowsRegister();
+      Info.setFlagOutputCCUpperBound(2);
       return true;
     }
     return false;
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
@@ -2601,7 +2601,7 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
               const llvm::ArrayRef<LValue> ResultRegDests,
               const llvm::ArrayRef<QualType> ResultRegQualTys,
               const llvm::BitVector &ResultTypeRequiresCast,
-              const llvm::BitVector &ResultRegIsFlagReg) {
+              const std::vector<unsigned> &ResultRegIsFlagReg) {
   CGBuilderTy &Builder = CGF.Builder;
   CodeGenModule &CGM = CGF.CGM;
   llvm::LLVMContext &CTX = CGF.getLLVMContext();
@@ -2628,14 +2628,7 @@ EmitAsmStores(CodeGenFunction &CGF, const AsmStmt &S,
       // observed for select_cc on SystemZ unit tests for flag output operands.
       // For some cases for br_cc, generated IR was weird. e.g. switch table
       // for simple simple comparison terms for br_cc.
-      StringRef Name;
-      if (const GCCAsmStmt *GAS = dyn_cast<GCCAsmStmt>(&S))
-        Name = GAS->getOutputName(i);
-      TargetInfo::ConstraintInfo Info(S.getOutputConstraint(i), Name);
-      bool IsValid = CGF.getTarget().validateOutputConstraint(Info);
-      (void)IsValid;
-      assert(IsValid && "Failed to parse flag output operand constraint");
-      unsigned CCUpperBound = Info.getFlagOutputCCUpperBound();
+      unsigned CCUpperBound = ResultRegIsFlagReg[i];
       llvm::Constant *CCUpperBoundConst =
           llvm::ConstantInt::get(Tmp->getType(), CCUpperBound);
       llvm::Value *IsBooleanValue =
@@ -2766,7 +2759,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
   std::vector<llvm::Type *> ArgElemTypes;
   std::vector<llvm::Value*> Args;
   llvm::BitVector ResultTypeRequiresCast;
-  llvm::BitVector ResultRegIsFlagReg;
+  std::vector<unsigned> ResultRegIsFlagReg;
 
   // Keep track of inout constraints.
   std::string InOutConstraints;
@@ -2824,8 +2817,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
       ResultRegQualTys.push_back(QTy);
       ResultRegDests.push_back(Dest);
 
-      bool IsFlagReg = llvm::StringRef(OutputConstraint).starts_with("{@cc");
-      ResultRegIsFlagReg.push_back(IsFlagReg);
+      ResultRegIsFlagReg.push_back(Info.getFlagOutputCCUpperBound());
 
       llvm::Type *Ty = ConvertTypeForMem(QTy);
       const bool RequiresCast = Info.allowsRegister() &&
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5107,9 +5107,6 @@ class TargetLowering : public TargetLoweringBase {
                                             std::vector<SDValue> &Ops,
                                             SelectionDAG &DAG) const;
 
-  // Lower switch statement for flag output operand with SRL/IPM Sequence.
-  virtual bool canLowerSRL_IPM_Switch(SDValue Cond) const;
-
   // Lower custom output constraints. If invalid, return SDValue().
   virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Glue,
                                               const SDLoc &DL,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2837,34 +2837,7 @@ void SelectionDAGBuilder::visitBr(const BranchInst &I) {
       Opcode = Instruction::And;
     else if (match(BOp, m_LogicalOr(m_Value(BOp0), m_Value(BOp1))))
       Opcode = Instruction::Or;
-    auto &TLI = DAG.getTargetLoweringInfo();
-    const auto checkSRLIPM = [&TLI](const SDValue &Op) {
-      if (!Op.getNumOperands())
-        return false;
-      SDValue OpVal = Op.getOperand(0);
-      SDNode *N = OpVal.getNode();
-      if (N && N->getOpcode() == ISD::SRL)
-        return TLI.canLowerSRL_IPM_Switch(OpVal);
-      else if (N && OpVal.getNumOperands() &&
-               (N->getOpcode() == ISD::AND || N->getOpcode() == ISD::OR)) {
-        SDValue OpVal1 = OpVal.getOperand(0);
-        SDNode *N1 = OpVal1.getNode();
-        if (N1 && N1->getOpcode() == ISD::SRL)
-          return TLI.canLowerSRL_IPM_Switch(OpVal1);
-      }
-      return false;
-    };
-    // Incoming IR here is straight line code, FindMergedConditions splits
-    // condition code sequence across Basic Block. DAGCombiner can't combine
-    // across Basic Block. Identify SRL/IPM/CC sequence for SystemZ and avoid
-    // transformation in FindMergedConditions.
-    bool BrSrlIPM = false;
-    if (NodeMap.count(BOp0) && NodeMap[BOp0].getNode()) {
-      BrSrlIPM |= checkSRLIPM(getValue(BOp0));
-      if (NodeMap.count(BOp1) && NodeMap[BOp1].getNode())
-        BrSrlIPM &= checkSRLIPM(getValue(BOp1));
-    }
-    if (Opcode && !BrSrlIPM &&
+    if (Opcode &&
         !(match(BOp0, m_ExtractElt(m_Value(Vec), m_Value())) &&
           match(BOp1, m_ExtractElt(m_Specific(Vec), m_Value()))) &&
         !shouldKeepJumpConditionsTogether(
@@ -12138,36 +12111,19 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
       const APInt &SmallValue = Small.Low->getValue();
       const APInt &BigValue = Big.Low->getValue();
 
-      // Incoming IR is switch table.Identify SRL/IPM/CC sequence for SystemZ
-      // and we want to avoid splitting condition code sequence across basic
-      // block for cases like (CC == 0) || (CC == 2) || (CC == 3), or
-      // (CC == 0) || (CC == 1) ^ (CC == 3), there could potentially be
-      // more cases like this.
-      const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-      bool IsSrlIPM = false;
-      if (NodeMap.count(Cond) && NodeMap[Cond].getNode())
-        IsSrlIPM = TLI.canLowerSRL_IPM_Switch(getValue(Cond));
       // Check that there is only one bit different.
       APInt CommonBit = BigValue ^ SmallValue;
-      if (CommonBit.isPowerOf2() || IsSrlIPM) {
+      if (CommonBit.isPowerOf2()) {
         SDValue CondLHS = getValue(Cond);
         EVT VT = CondLHS.getValueType();
         SDLoc DL = getCurSDLoc();
         SDValue Cond;
 
-        if (CommonBit.isPowerOf2()) {
-          SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
-                                   DAG.getConstant(CommonBit, DL, VT));
-          Cond = DAG.getSetCC(DL, MVT::i1, Or,
-                              DAG.getConstant(BigValue | SmallValue, DL, VT),
-                              ISD::SETEQ);
-        } else if (IsSrlIPM && BigValue == 3 && SmallValue == 0) {
-          SDValue SetCC =
-              DAG.getSetCC(DL, MVT::i32, CondLHS,
-                           DAG.getConstant(SmallValue, DL, VT), ISD::SETEQ);
-          Cond = DAG.getSetCC(DL, MVT::i32, SetCC,
-                              DAG.getConstant(BigValue, DL, VT), ISD::SETEQ);
-        }
+        SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
+                                 DAG.getConstant(CommonBit, DL, VT));
+        Cond = DAG.getSetCC(DL, MVT::i1, Or,
+                            DAG.getConstant(BigValue | SmallValue, DL, VT),
+                            ISD::SETEQ);
 
         // Update successor info.
         // Both Small and Big will jump to Small.BB, so we sum up the
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5576,10 +5576,6 @@ const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
   return nullptr;
 }
 
-bool TargetLowering::canLowerSRL_IPM_Switch(SDValue Cond) const {
-  return false;
-}
-
 SDValue TargetLowering::LowerAsmOutputForConstraint(
     SDValue &Chain, SDValue &Glue, const SDLoc &DL,
     const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const {
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -24,6 +24,7 @@
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/IntrinsicsS390.h"
+#include "llvm/IR/PatternMatch.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/KnownBits.h"
@@ -8694,23 +8695,37 @@ SystemZTargetLowering::combineSELECT_CC_CCIPMMask(SDNode *N,
   return std::nullopt;
 }
 
-bool SystemZTargetLowering::canLowerSRL_IPM_Switch(SDValue Cond) const {
-  auto *SRL = Cond.getNode();
-  if (!SRL || SRL->getOpcode() != ISD::SRL)
-    return false;
-  auto *SRLCount = dyn_cast<ConstantSDNode>(SRL->getOperand(1));
-  if (!SRLCount || SRLCount->getZExtValue() != SystemZ::IPM_CC)
-    return false;
-  auto *IPM = SRL->getOperand(0).getNode();
-  if (!IPM || IPM->getOpcode() != SystemZISD::IPM)
-    return false;
-  auto IPMOp0 = IPM->getOperand(0).getNode();
-  if (!IPMOp0 || IPMOp0->getNumOperands() < 2)
-    return false;
-  auto RN = dyn_cast<RegisterSDNode>(IPMOp0->getOperand(1));
-  if (!RN || !RN->getReg().isPhysical() || RN->getReg() != SystemZ::CC)
+// Merging versus split in multiple branches cost.
+TargetLoweringBase::CondMergingParams
+SystemZTargetLowering::getJumpConditionMergingParams(Instruction::BinaryOps Opc,
+                                                     const Value *Lhs,
+                                                     const Value *Rhs) const {
+  const auto isFlagOutOpCC = [](const Value *V) {
+    using namespace llvm::PatternMatch;
+    const Value *RHSVal;
+    const APInt *RHSC;
+    if (const auto *I = dyn_cast<Instruction>(V)) {
+      if (match(I->getOperand(0), m_And(m_Value(RHSVal), m_APInt(RHSC))) ||
+          match(I, m_Cmp(m_Value(RHSVal), m_APInt(RHSC)))) {
+        if (const auto *CB = dyn_cast<CallBase>(RHSVal)) {
+          if (CB->isInlineAsm()) {
+            const InlineAsm *IA = cast<InlineAsm>(CB->getCalledOperand());
+            return IA &&
+                   IA->getConstraintString().find("{@cc}") != std::string::npos;
+          }
+        }
+      }
+    }
     return false;
-  return true;
+  };
+  // Pattern (ICmp %asm) or (ICmp (And %asm)).
+  // Cost of longest dependency chain (ICmp, And) is 2. CostThreshold or
+  // BaseCost can be set >=2. If cost of instruction <= CostThreshold
+  // conditionals will be merged or else conditionals will be split.
+  if (isFlagOutOpCC(Lhs) && isFlagOutOpCC(Rhs))
+    return {3, 0, -1};
+  // Default.
+  return {-1, -1, -1};
 }
 
 SDValue SystemZTargetLowering::combineBR_CCMASK(
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -521,8 +521,10 @@ class SystemZTargetLowering : public TargetLowering {
 
   const char *getTargetNodeName(unsigned Opcode) const override;
 
-  // Check for if flag output operands has SRL/IPM Sequence.
-  bool canLowerSRL_IPM_Switch(SDValue Cond) const override;
+  // This function currently returns cost for srl/ipm/cc sequence for merging.
+  CondMergingParams
+  getJumpConditionMergingParams(Instruction::BinaryOps Opc, const Value *Lhs,
+                                const Value *Rhs) const override;
 
   // Handle Lowering flag assembly outputs.
   SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
diff --git a/llvm/test/CodeGen/SystemZ/flag_output_operand_ccand_not.ll b/llvm/test/CodeGen/SystemZ/flag_output_operand_ccand_not.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; Test Flag Output Operands with 14 combinations of CCMASK and optimizations.
 ; This test negate of flag_output_operand_ccand, e.g
-; CC != 0 && cc !- 1 && cc != 2 for AND for 3 three different functions, 
+; CC != 0 && cc != 1 && cc != 2 for AND for three different functions,
 ; including two test cases from heiko.
 
 ; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -O2 | FileCheck %s
@@ -555,6 +555,8 @@ if.end:                                           ; preds = %if.then, %entry
 }
 
 ; Test CC != 0 && CC != 3.
+; TODO: DAGCombiner is not able to optimize srl/ipm/cc sequence because of
+; switch table created by simplifyBranchOnICmpChain.
 define void @bar_03(){
 ; CHECK-LABEL: bar_03:
 ; CHECK:       # %bb.0: # %entry
@@ -563,8 +565,13 @@ define void @bar_03(){
 ; CHECK-NEXT:    alsi 0(%r1), -1
 ; CHECK-EMPTY:
 ; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    ipm %r0
+; CHECK-NEXT:    ber %r14
+; CHECK-NEXT:  .LBB22_1: # %entry
+; CHECK-NEXT:    srl %r0, 28
+; CHECK-NEXT:    chi %r0, 3
 ; CHECK-NEXT:    jglh dummy@PLT
-; CHECK-NEXT:  .LBB22_1: # %if.end
+; CHECK-NEXT:  .LBB22_2: # %if.end
 ; CHECK-NEXT:    br %r14
 entry:
   %0 = tail call i32 asm "       alsi    $1,-1\0A", "={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull elementtype(i32) @a) #3
diff --git a/llvm/test/CodeGen/SystemZ/flag_output_operand_ccmixed_eq_noteq.ll b/llvm/test/CodeGen/SystemZ/flag_output_operand_ccmixed_eq_noteq.ll
diff --git a/llvm/test/CodeGen/SystemZ/flag_output_operand_ccmixed_not.ll b/llvm/test/CodeGen/SystemZ/flag_output_operand_ccmixed_not.ll
diff --git a/llvm/test/CodeGen/SystemZ/flag_output_operand_ccor.ll b/llvm/test/CodeGen/SystemZ/flag_output_operand_ccor.ll
diff --git a/llvm/test/CodeGen/SystemZ/flag_output_operand_ccxor.ll b/llvm/test/CodeGen/SystemZ/flag_output_operand_ccxor.ll
diff --git a/llvm/test/CodeGen/SystemZ/flag_output_operand_ccxor_eq_noteq.ll b/llvm/test/CodeGen/SystemZ/flag_output_operand_ccxor_eq_noteq.ll
diff --git a/llvm/test/CodeGen/SystemZ/flag_output_operand_ccxor_not.ll b/llvm/test/CodeGen/SystemZ/flag_output_operand_ccxor_not.ll

Original file line number	Diff line number	Diff line change
`@@ -1119,7 +1119,7 @@ class TargetInfo : public TransferrableTargetInfo,`
`1119`	`1119`	`public:`
`1120`	`1120`	`ConstraintInfo(StringRef ConstraintStr, StringRef Name)`
`1121`	`1121`	`: Flags(0), TiedOperand(-1), ConstraintStr(ConstraintStr.str()),`
`1122`		`- Name(Name.str()), FlagOutputCCUpperBound(2) {`
	`1122`	`+ Name(Name.str()), FlagOutputCCUpperBound(0) {`
`1123`	`1123`	`ImmRange.Min = ImmRange.Max = 0;`
`1124`	`1124`	`ImmRange.isConstrained = false;`
`1125`	`1125`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1552,6 +1552,7 @@ bool AArch64TargetInfo::validateAsmConstraint(`
`1552`	`1552`	`if (const unsigned Len = matchAsmCCConstraint(Name)) {`
`1553`	`1553`	`Name += Len - 1;`
`1554`	`1554`	`Info.setAllowsRegister();`
	`1555`	`+ Info.setFlagOutputCCUpperBound(2);`
`1555`	`1556`	`return true;`
`1556`	`1557`	`}`
`1557`	`1558`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1580,6 +1580,7 @@ bool X86TargetInfo::validateAsmConstraint(`
`1580`	`1580`	`if (auto Len = matchAsmCCConstraint(Name)) {`
`1581`	`1581`	`Name += Len - 1;`
`1582`	`1582`	`Info.setAllowsRegister();`
	`1583`	`+ Info.setFlagOutputCCUpperBound(2);`
`1583`	`1584`	`return true;`
`1584`	`1585`	`}`
`1585`	`1586`	`return false;`