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[RISCV][MC] Add assembler support for XRivosVisni
This implements assembler support for the XRivosVisni custom/vendor extension from Rivos Inc. which is defined in: https://github.com/rivosinc/rivos-custom-extensions (See src/xrivosvisni.adoc) Codegen support will follow in a separate change.
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7 files changed

+122
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -204,6 +204,7 @@
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// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Small Integer New)
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// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
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// CHECK-EMPTY:
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// CHECK-NEXT: Supported Profiles

‎llvm/docs/RISCVUsage.rst‎

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@@ -468,6 +468,9 @@ The current vendor extensions supported are:
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``Xmipslsp``
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LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
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``experimental-XRivosVisni``
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LLVM implements `version 0.1 of the Rivos Vector Integer Small New Instructions extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
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``experimental-XRivosVizip``
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LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
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‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -622,6 +622,10 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const {
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#define TRY_TO_DECODE_FEATURE_ANY(FEATURES, DECODER_TABLE, DESC) \
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TRY_TO_DECODE((STI.getFeatureBits() & (FEATURES)).any(), DECODER_TABLE, DESC)
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static constexpr FeatureBitset XRivosFeatureGroup = {
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RISCV::FeatureVendorXRivosVisni, RISCV::FeatureVendorXRivosVizip,
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};
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static constexpr FeatureBitset XqciFeatureGroup = {
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RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
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RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
@@ -717,12 +721,11 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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"CORE-V SIMD extensions");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
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"CORE-V Immediate Branching");
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TRY_TO_DECODE_FEATURE_ANY(XqciFeatureGroup, DecoderTableXqci32,
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"Qualcomm uC Extensions");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXRivosVizip, DecoderTableXRivos32,
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"Rivos");
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TRY_TO_DECODE_FEATURE_ANY(XRivosFeatureGroup, DecoderTableXRivos32,
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"Rivos");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32");
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‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1376,6 +1376,13 @@ def HasVendorXqcilo
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// Rivos Extension(s)
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def FeatureVendorXRivosVisni
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: RISCVExperimentalExtension<0, 1, "Rivos Vector Small Integer New">;
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def HasVendorXRivosVisni
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: Predicate<"Subtarget->hasVendorXRivosVisni()">,
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AssemblerPredicate<(all_of FeatureVendorXRivosVisni),
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"'XRivosVizisni' (Rivos Vector Small Integer New)">;
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def FeatureVendorXRivosVizip
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: RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
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def HasVendorXRivosVizip

‎llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td‎

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@@ -10,6 +10,46 @@
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//
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//===----------------------------------------------------------------------===//
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class RVInstVXI<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> imm;
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bits<5> rs1;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = imm;
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let Inst{19-15} = rs1;
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let Inst{14-12} = opv.Value;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstXVI<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> imm;
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bits<5> vs2;
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bits<5> rd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = imm;
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let Inst{14-12} = opv.Value;
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let Inst{11-7} = rd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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//===----------------------------------------------------------------------===//
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// XRivosVizip
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//===----------------------------------------------------------------------===//
@@ -25,3 +65,27 @@ defm RI_VZIP2B_V : VALU_IV_V<"ri.vzip2b", 0b010100>;
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defm RI_VUNZIP2A_V : VALU_IV_V<"ri.vunzip2a", 0b001000>;
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defm RI_VUNZIP2B_V : VALU_IV_V<"ri.vunzip2b", 0b011000>;
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}
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//===----------------------------------------------------------------------===//
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// XRivosVisni
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXRivosVisni], DecoderNamespace = "XRivos",
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Inst<6-0> = OPC_CUSTOM_2.Value, mayLoad = false, mayStore = false,
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hasSideEffects = false in {
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let isReMaterializable = 1, isAsCheapAsAMove = 1, vm = 0, vs2=0 in
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def RI_VZERO : RVInstV<0b000000, 0b00000, OPCFG, (outs VR:$vd),
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(ins), "ri.vzero", "$vd">;
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let vm = 0, Constraints = "$vd = $vd_wb", RVVConstraint = NoConstraint in
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def RI_VINSERT : RVInstVXI<0b010000, OPMVX, (outs VR:$vd_wb),
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(ins VR:$vd, GPR:$rs1, uimm5:$imm),
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"ri.vinsert.v.x", "$vd, $rs1, $imm">;
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let vm = 1, RVVConstraint = NoConstraint in
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def RI_VEXTRACT : RVInstXVI<0b010111, OPMVV, (outs GPR:$rd),
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(ins VR:$vs2, uimm5:$imm),
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"ri.vextract.x.v", "$rd, $vs2, $imm">;
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}

‎llvm/test/MC/RISCV/xrivosvisni-valid.s‎

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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvisni -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvisni < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xrivosvisni -M no-aliases --no-print-imm-hex -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvisni -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvisni < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xrivosvisni -M no-aliases --no-print-imm-hex -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# CHECK-ASM-AND-OBJ: ri.vzero v1
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# CHECK-ASM: encoding: [0xdb,0x70,0x00,0x00]
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ri.vzero v1
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# CHECK-ASM-AND-OBJ: vzero v2
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# CHECK-ASM: encoding: [0x5b,0x71,0x00,0x00]
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ri.vzero v2
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# CHECK-ASM-AND-OBJ: vzero v3
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# CHECK-ASM: encoding: [0xdb,0x71,0x00,0x00]
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ri.vzero v3
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# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v0, zero, 0
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# CHECK-ASM: encoding: [0x5b,0x60,0x00,0x40]
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ri.vinsert.v.x v0, x0, 0
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# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v1, s4, 13
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# CHECK-ASM: encoding: [0xdb,0x60,0xda,0x40]
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ri.vinsert.v.x v1, x20, 13
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# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v1, zero, 1
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# CHECK-ASM: encoding: [0xdb,0x60,0x10,0x40]
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ri.vinsert.v.x v1, x0, 1
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# CHECK-ASM-AND-OBJ: ri.vinsert.v.x v23, ra, 1
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# CHECK-ASM: encoding: [0xdb,0xeb,0x10,0x40]
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ri.vinsert.v.x v23, x1, 1
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# CHECK-ASM-AND-OBJ: ri.vextract.x.v s4, v1, 13
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# CHECK-ASM: encoding: [0x5b,0xaa,0x16,0x5e]
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ri.vextract.x.v x20, v1, 13
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# CHECK-ASM-AND-OBJ: ri.vextract.x.v s5, v2, 31
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# CHECK-ASM: encoding: [0xdb,0xaa,0x2f,0x5e]
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ri.vextract.x.v x21, v2, 31

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp‎

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@@ -1130,6 +1130,7 @@ Experimental extensions
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xqcilo 0.2
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xqcilsm 0.2
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xqcisls 0.2
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xrivosvisni 0.1
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xrivosvizip 0.1
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Supported Profiles

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