[RISCV] Add a generic OOO CPU (#120712)

We add a generic out-of-order CPU model here just like what GCC
has done.
    
People may use this model to evaluate some optimizations, and more
importantly, people can use this model as a template to customize
their own CPU models.
    
The design (units, cycles, ...) of this model is random so don't
take it seriously.

Author: wangpc-pp

clang/docs/ReleaseNotes.rst

@@ -217,6 +217,8 @@ LoongArch Support
 RISC-V Support
 ^^^^^^^^^^^^^^
 
+- Add support for `-mtune=generic-ooo` (a generic out-of-order model).
+
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 

clang/test/Misc/target-invalid-cpu-note/riscv.c

@@ -66,6 +66,7 @@
 // TUNE-RISCV32-SAME: {{^}}, syntacore-scr4-rv32
 // TUNE-RISCV32-SAME: {{^}}, syntacore-scr5-rv32
 // TUNE-RISCV32-SAME: {{^}}, generic
+// TUNE-RISCV32-SAME: {{^}}, generic-ooo
 // TUNE-RISCV32-SAME: {{^}}, rocket
 // TUNE-RISCV32-SAME: {{^}}, sifive-7-series
 // TUNE-RISCV32-SAME: {{$}}
@@ -96,6 +97,7 @@
 // TUNE-RISCV64-SAME: {{^}}, veyron-v1
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
 // TUNE-RISCV64-SAME: {{^}}, generic
+// TUNE-RISCV64-SAME: {{^}}, generic-ooo
 // TUNE-RISCV64-SAME: {{^}}, rocket
 // TUNE-RISCV64-SAME: {{^}}, sifive-7-series
 // TUNE-RISCV64-SAME: {{$}}

llvm/lib/Target/RISCV/RISCV.td

@@ -45,7 +45,7 @@ include "RISCVMacroFusion.td"
 //===----------------------------------------------------------------------===//
 // RISC-V Scheduling Models
 //===----------------------------------------------------------------------===//
-
+include "RISCVSchedGenericOOO.td"
 include "RISCVSchedMIPSP8700.td"
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -103,6 +103,8 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
 // Support generic for compatibility with other targets. The triple will be used
 // to change to the appropriate rv32/rv64 version.
 def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
+def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
+                  GenericTuneInfo;
 
 def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
                                      MIPSP8700Model,