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davemgreendavemgreen
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Add strictfp to strict-intrinsics.ll tests.
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‎llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll‎

Lines changed: 22 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -o - %s | FileCheck %s
33

4-
define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) {
4+
define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) #0 {
55
; CHECK-LABEL: test_vaddq_f16:
66
; CHECK: @ %bb.0: @ %entry
77
; CHECK-NEXT: vadd.f16 q0, q0, q1
@@ -11,7 +11,7 @@ entry:
1111
ret <8 x half> %0
1212
}
1313

14-
define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32(<4 x float> %a, <4 x float> %b) {
14+
define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32(<4 x float> %a, <4 x float> %b) #0 {
1515
; CHECK-LABEL: test_vaddq_f32:
1616
; CHECK: @ %bb.0: @ %entry
1717
; CHECK-NEXT: vadd.f32 q0, q0, q1
@@ -21,7 +21,7 @@ entry:
2121
ret <4 x float> %0
2222
}
2323

24-
define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) {
24+
define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) #0 {
2525
; CHECK-LABEL: test_vsubq_f16:
2626
; CHECK: @ %bb.0: @ %entry
2727
; CHECK-NEXT: vsub.f16 q0, q0, q1
@@ -31,7 +31,7 @@ entry:
3131
ret <8 x half> %0
3232
}
3333

34-
define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32(<4 x float> %a, <4 x float> %b) {
34+
define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32(<4 x float> %a, <4 x float> %b) #0 {
3535
; CHECK-LABEL: test_vsubq_f32:
3636
; CHECK: @ %bb.0: @ %entry
3737
; CHECK-NEXT: vsub.f32 q0, q0, q1
@@ -41,7 +41,7 @@ entry:
4141
ret <4 x float> %0
4242
}
4343

44-
define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16(<8 x half> %a, <8 x half> %b) {
44+
define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16(<8 x half> %a, <8 x half> %b) #0 {
4545
; CHECK-LABEL: test_vmulq_f16:
4646
; CHECK: @ %bb.0: @ %entry
4747
; CHECK-NEXT: vmul.f16 q0, q0, q1
@@ -51,7 +51,7 @@ entry:
5151
ret <8 x half> %0
5252
}
5353

54-
define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> %a, <4 x float> %b) {
54+
define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> %a, <4 x float> %b) #0 {
5555
; CHECK-LABEL: test_vmulq_f32:
5656
; CHECK: @ %bb.0: @ %entry
5757
; CHECK-NEXT: vmul.f32 q0, q0, q1
@@ -64,7 +64,7 @@ entry:
6464

6565

6666

67-
define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16_splat(<8 x half> %a, half %b) {
67+
define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16_splat(<8 x half> %a, half %b) #0 {
6868
; CHECK-LABEL: test_vaddq_f16_splat:
6969
; CHECK: @ %bb.0: @ %entry
7070
; CHECK-NEXT: vmov.f16 r0, s4
@@ -77,7 +77,7 @@ entry:
7777
ret <8 x half> %0
7878
}
7979

80-
define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32_splat(<4 x float> %a, float %b) {
80+
define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32_splat(<4 x float> %a, float %b) #0 {
8181
; CHECK-LABEL: test_vaddq_f32_splat:
8282
; CHECK: @ %bb.0: @ %entry
8383
; CHECK-NEXT: vmov r0, s4
@@ -90,7 +90,7 @@ entry:
9090
ret <4 x float> %0
9191
}
9292

93-
define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16_splat(<8 x half> %a, half %b) {
93+
define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16_splat(<8 x half> %a, half %b) #0 {
9494
; CHECK-LABEL: test_vsubq_f16_splat:
9595
; CHECK: @ %bb.0: @ %entry
9696
; CHECK-NEXT: vmov.f16 r0, s4
@@ -103,7 +103,7 @@ entry:
103103
ret <8 x half> %0
104104
}
105105

106-
define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32_splat(<4 x float> %a, float %b) {
106+
define arm_aapcs_vfpcc <4 x float> @test_vsubq_f32_splat(<4 x float> %a, float %b) #0 {
107107
; CHECK-LABEL: test_vsubq_f32_splat:
108108
; CHECK: @ %bb.0: @ %entry
109109
; CHECK-NEXT: vmov r0, s4
@@ -116,7 +116,7 @@ entry:
116116
ret <4 x float> %0
117117
}
118118

119-
define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16_splat(<8 x half> %a, half %b) {
119+
define arm_aapcs_vfpcc <8 x half> @test_vmulq_f16_splat(<8 x half> %a, half %b) #0 {
120120
; CHECK-LABEL: test_vmulq_f16_splat:
121121
; CHECK: @ %bb.0: @ %entry
122122
; CHECK-NEXT: vmov.f16 r0, s4
@@ -129,7 +129,7 @@ entry:
129129
ret <8 x half> %0
130130
}
131131

132-
define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32_splat(<4 x float> %a, float %b) {
132+
define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32_splat(<4 x float> %a, float %b) #0 {
133133
; CHECK-LABEL: test_vmulq_f32_splat:
134134
; CHECK: @ %bb.0: @ %entry
135135
; CHECK-NEXT: vmov r0, s4
@@ -142,7 +142,7 @@ entry:
142142
ret <4 x float> %0
143143
}
144144

145-
define arm_aapcs_vfpcc <4 x float> @fma_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) {
145+
define arm_aapcs_vfpcc <4 x float> @fma_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) #0 {
146146
; CHECK-LABEL: fma_v4f32:
147147
; CHECK: @ %bb.0: @ %entry
148148
; CHECK-NEXT: vfma.f32 q0, q1, q2
@@ -152,7 +152,7 @@ entry:
152152
ret <4 x float> %0
153153
}
154154

155-
define arm_aapcs_vfpcc <8 x half> @fma_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) {
155+
define arm_aapcs_vfpcc <8 x half> @fma_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) #0 {
156156
; CHECK-LABEL: fma_v8f16:
157157
; CHECK: @ %bb.0: @ %entry
158158
; CHECK-NEXT: vfma.f16 q0, q1, q2
@@ -162,7 +162,7 @@ entry:
162162
ret <8 x half> %0
163163
}
164164

165-
define arm_aapcs_vfpcc <4 x float> @fma_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) {
165+
define arm_aapcs_vfpcc <4 x float> @fma_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) #0 {
166166
; CHECK-LABEL: fma_n_v8f16:
167167
; CHECK: @ %bb.0: @ %entry
168168
; CHECK-NEXT: vmov r0, s8
@@ -175,7 +175,7 @@ entry:
175175
ret <4 x float> %0
176176
}
177177

178-
define arm_aapcs_vfpcc <8 x half> @fma_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) {
178+
define arm_aapcs_vfpcc <8 x half> @fma_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) #0 {
179179
; CHECK-LABEL: fma_n_v4f32:
180180
; CHECK: @ %bb.0: @ %entry
181181
; CHECK-NEXT: vmov.f16 r0, s8
@@ -188,7 +188,7 @@ entry:
188188
ret <8 x half> %0
189189
}
190190

191-
define arm_aapcs_vfpcc <4 x float> @fms_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) {
191+
define arm_aapcs_vfpcc <4 x float> @fms_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) #0 {
192192
; CHECK-LABEL: fms_v4f32:
193193
; CHECK: @ %bb.0: @ %entry
194194
; CHECK-NEXT: vfms.f32 q0, q1, q2
@@ -199,7 +199,7 @@ entry:
199199
ret <4 x float> %0
200200
}
201201

202-
define arm_aapcs_vfpcc <8 x half> @fms_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) {
202+
define arm_aapcs_vfpcc <8 x half> @fms_v8f16(<8 x half> %dst, <8 x half> %s1, <8 x half> %s2) #0 {
203203
; CHECK-LABEL: fms_v8f16:
204204
; CHECK: @ %bb.0: @ %entry
205205
; CHECK-NEXT: vfms.f16 q0, q1, q2
@@ -210,7 +210,7 @@ entry:
210210
ret <8 x half> %0
211211
}
212212

213-
define arm_aapcs_vfpcc <4 x float> @fms_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) {
213+
define arm_aapcs_vfpcc <4 x float> @fms_n_v8f16(<4 x float> %s1, <4 x float> %s2, float %s3) #0 {
214214
; CHECK-LABEL: fms_n_v8f16:
215215
; CHECK: @ %bb.0: @ %entry
216216
; CHECK-NEXT: vmov r0, s8
@@ -225,7 +225,7 @@ entry:
225225
ret <4 x float> %0
226226
}
227227

228-
define arm_aapcs_vfpcc <8 x half> @fms_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) {
228+
define arm_aapcs_vfpcc <8 x half> @fms_n_v4f32(<8 x half> %s1, <8 x half> %s2, half %s3) #0 {
229229
; CHECK-LABEL: fms_n_v4f32:
230230
; CHECK: @ %bb.0: @ %entry
231231
; CHECK-NEXT: vmov.f16 r0, s8
@@ -239,3 +239,5 @@ entry:
239239
%0 = tail call <8 x half> @llvm.arm.mve.fma.v8f16(<8 x half> %c, <8 x half> %sp, <8 x half> %s1)
240240
ret <8 x half> %0
241241
}
242+
243+
attributes #0 = { strictfp }

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