Remove unused intrinsics, fix sle[u] issue by zext instruction.

Author: realqhc

clang/lib/CodeGen/CGBuiltin.cpp

@@ -22371,9 +22371,11 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
     return Builder.CreateZExt(Builder.CreateTrunc(Ops[0], Int16Ty), Int32Ty,
                               "exthz");
   case RISCV::BI__builtin_riscv_cv_alu_slet:
-    return Builder.CreateICmpSLE(Ops[0], Ops[1], "sle");
+    return Builder.CreateZExt(Builder.CreateICmpSLE(Ops[0], Ops[1]), Int32Ty,
+                              "sle");
   case RISCV::BI__builtin_riscv_cv_alu_sletu:
-    return Builder.CreateICmpULE(Ops[0], Ops[1], "sleu");
+    return Builder.CreateZExt(Builder.CreateICmpULE(Ops[0], Ops[1]), Int32Ty,
+                              "sleu");
   case RISCV::BI__builtin_riscv_cv_alu_subN:
     ID = Intrinsic::riscv_cv_alu_subN;
     break;

clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c

@@ -19,8 +19,8 @@
 // CHECK-NEXT:    store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4
 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4
 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4
-// CHECK-NEXT:    [[SLE_I:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
-// CHECK-NEXT:    [[CONV_I:%.*]] = sext i1 [[SLE_I]] to i32
+// CHECK-NEXT:    [[TMP4:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
+// CHECK-NEXT:    [[CONV_I:%.*]] = sext i1 [[TMP4]] to i32
 // CHECK-NEXT:    ret i32 [[CONV_I]]
 //
 int test_alu_slet(int32_t a, int32_t b) {
@@ -41,8 +41,8 @@ int test_alu_slet(int32_t a, int32_t b) {
 // CHECK-NEXT:    store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4
 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4
 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4
-// CHECK-NEXT:    [[SLEU_I:%.*]] = icmp ule i32 [[TMP2]], [[TMP3]]
-// CHECK-NEXT:    [[CONV_I:%.*]] = sext i1 [[SLEU_I]] to i32
+// CHECK-NEXT:    [[TMP4:%.*]] = icmp ule i32 [[TMP2]], [[TMP3]]
+// CHECK-NEXT:    [[CONV_I:%.*]] = sext i1 [[TMP4]] to i32
 // CHECK-NEXT:    ret i32 [[CONV_I]]
 //
 int test_alu_sletu(uint32_t a, uint32_t b) {

clang/test/CodeGen/RISCV/riscv-xcvalu.c

@@ -18,35 +18,31 @@ int test_abs(int a) {
 
 // CHECK-LABEL: @test_alu_slet(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
 // CHECK-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// CHECK-NEXT:    [[SLE:%.*]] = icmp sle i32 [[TMP0]], [[TMP1]]
-// CHECK-NEXT:    store i1 [[SLE]], ptr [[RETVAL]], align 4
-// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp sle i32 [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SLE:%.*]] = zext i1 [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[SLE]]
 //
 int test_alu_slet(int32_t a, int32_t b) {
   return __builtin_riscv_cv_alu_slet(a, b);
 }
 
 // CHECK-LABEL: @test_alu_sletu(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
 // CHECK-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
-// CHECK-NEXT:    [[SLEU:%.*]] = icmp ule i32 [[TMP0]], [[TMP1]]
-// CHECK-NEXT:    store i1 [[SLEU]], ptr [[RETVAL]], align 4
-// CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK-NEXT:    ret i32 [[TMP2]]
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp ule i32 [[TMP0]], [[TMP1]]
+// CHECK-NEXT:    [[SLEU:%.*]] = zext i1 [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[SLEU]]
 //
 int test_alu_sletu(uint32_t a, uint32_t b) {
   return __builtin_riscv_cv_alu_sletu(a, b);

llvm/include/llvm/IR/IntrinsicsRISCVXCV.td

@@ -59,16 +59,6 @@ let TargetPrefix = "riscv" in {
                             [IntrNoMem, IntrWillReturn, IntrSpeculatable,
                             ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
 
-  def int_riscv_cv_alu_slet  : ScalarCoreVAluGprGprIntrinsic;
-  def int_riscv_cv_alu_sletu : ScalarCoreVAluGprGprIntrinsic;
-  def int_riscv_cv_alu_min   : ScalarCoreVAluGprGprIntrinsic;
-  def int_riscv_cv_alu_minu  : ScalarCoreVAluGprGprIntrinsic;
-  def int_riscv_cv_alu_max   : ScalarCoreVAluGprGprIntrinsic;
-  def int_riscv_cv_alu_maxu  : ScalarCoreVAluGprGprIntrinsic;
-  def int_riscv_cv_alu_exths : ScalarCoreVAluGprIntrinsic;
-  def int_riscv_cv_alu_exthz : ScalarCoreVAluGprIntrinsic;
-  def int_riscv_cv_alu_extbs : ScalarCoreVAluGprIntrinsic;
-  def int_riscv_cv_alu_extbz : ScalarCoreVAluGprIntrinsic;
   def int_riscv_cv_alu_clip   : ScalarCoreVAluGprGprIntrinsic;
   def int_riscv_cv_alu_clipu  : ScalarCoreVAluGprGprIntrinsic;
   def int_riscv_cv_alu_addN   : ScalarCoreVAluGprGprGprIntrinsic;