[RISCV] Support overlapping constraints

BeMg · BeMg · commit 7ef13811608d · 2025-06-19T23:24:05.000-07:00
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -41,6 +41,7 @@ class LiveRegMatrix {
   friend class LiveRegMatrixWrapperLegacy;
   friend class LiveRegMatrixAnalysis;
   const TargetRegisterInfo *TRI = nullptr;
+  const MachineRegisterInfo *MRI;
   LiveIntervals *LIS = nullptr;
   VirtRegMap *VRM = nullptr;
 
@@ -108,6 +109,12 @@ class LiveRegMatrix {
   InterferenceKind checkInterference(const LiveInterval &VirtReg,
                                      MCRegister PhysReg);
 
+  /// Check for target interference before assigning VirtReg to PhysReg.Add
+  /// commentMore actions
+  SmallVector<const LiveInterval *, 8>
+  getTargetInterferenceLiveI(const LiveInterval &VirtReg,
+                             MCRegister PhysReg) const;
+
   /// Check for interference in the segment [Start, End) that may prevent
   /// assignment to PhysReg. If this function returns true, there is
   /// interference in the segment [Start, End) of some other interval already
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -16,6 +16,7 @@
 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
 
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/iterator_range.h"
@@ -42,6 +43,7 @@ class RegScavenger;
 class VirtRegMap;
 class LiveIntervals;
 class LiveInterval;
+class LiveRange;
 class TargetRegisterClass {
 public:
   using iterator = const MCPhysReg *;
@@ -1230,6 +1232,20 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
     return false;
   }
 
+  virtual bool enableTargetInterference() const { return false; }
+
+  virtual BitVector getTargetInterferenceReg(const LiveInterval &VirtReg,
+                                             MCRegister PhysReg,
+                                             const MachineRegisterInfo *MRI,
+                                             const VirtRegMap *VRM) const {
+    return BitVector();
+  }
+
+  virtual bool needUpdateECSlot(const LiveRange &LR, LiveRange &newLR,
+                                const LiveIntervals &LIS) const {
+    return false;
+  }
+
   /// Some targets delay assigning the frame until late and use a placeholder
   /// to represent it earlier. This method can be used to identify the frame
   /// register placeholder.
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -60,6 +60,7 @@ bool LiveRegMatrixWrapperLegacy::runOnMachineFunction(MachineFunction &MF) {
 void LiveRegMatrix::init(MachineFunction &MF, LiveIntervals &pLIS,
                          VirtRegMap &pVRM) {
   TRI = MF.getSubtarget().getRegisterInfo();
+  MRI = &MF.getRegInfo();
   LIS = &pLIS;
   VRM = &pVRM;
 
@@ -83,6 +84,14 @@ void LiveRegMatrix::releaseMemory() {
   }
 }
 
+static LiveRange copyLiveRange(const LiveRange &LR) {
+  LiveRange NewLR;
+  for (auto Seg : LR.segments)
+    NewLR.addSegment(Seg);
+  NewLR.valnos.append(LR.vni_begin(), LR.vni_end());
+  return NewLR;
+}
+
 template <typename Callable>
 static bool foreachUnit(const TargetRegisterInfo *TRI,
                         const LiveInterval &VRegInterval, MCRegister PhysReg,
@@ -117,7 +126,12 @@ void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) {
   foreachUnit(
       TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {
         LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
-        Matrix[Unit].unify(VirtReg, Range);
+        LiveRange NewLR;
+        if (TRI->enableTargetInterference() &&
+            TRI->needUpdateECSlot(Range, NewLR = copyLiveRange(Range), *LIS))
+          Matrix[Unit].unify(VirtReg, NewLR);
+        else
+          Matrix[Unit].unify(VirtReg, Range);
         return false;
       });
 
@@ -134,7 +148,13 @@ void LiveRegMatrix::unassign(const LiveInterval &VirtReg) {
   foreachUnit(TRI, VirtReg, PhysReg,
               [&](unsigned Unit, const LiveRange &Range) {
                 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
-                Matrix[Unit].extract(VirtReg, Range);
+                LiveRange NewLR;
+                if (TRI->enableTargetInterference() &&
+                    TRI->needUpdateECSlot(Range, NewLR = copyLiveRange(Range),
+                                          *LIS))
+                  Matrix[Unit].extract(VirtReg, NewLR);
+                else
+                  Matrix[Unit].extract(VirtReg, Range);
                 return false;
               });
 
@@ -150,6 +170,31 @@ bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const {
   return false;
 }
 
+SmallVector<const LiveInterval *, 8>
+LiveRegMatrix::getTargetInterferenceLiveI(const LiveInterval &VirtReg,
+                                          MCRegister PhysReg) const {
+  SmallVector<const LiveInterval *, 8> LiveIs;
+  if (!TRI->enableTargetInterference())
+    return LiveIs;
+
+  BitVector IntfReg = TRI->getTargetInterferenceReg(VirtReg, PhysReg, MRI, VRM);
+
+  for (auto Reg : IntfReg.set_bits()) {
+    for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
+      LiveIntervalUnion LiveUnion = Matrix[*Units];
+      LiveIntervalUnion::ConstSegmentIter LiveUnionI = LiveUnion.begin();
+      while (LiveUnionI != LiveUnion.end()) {
+        const LiveRange *LiveR = *LiveUnionI;
+        LiveRange NewLiveR = copyLiveRange(*LiveR);
+        if (TRI->needUpdateECSlot(LiveR, NewLiveR, *LIS))
+          LiveIs.push_back(*LiveUnionI);
+        ++LiveUnionI;
+      }
+    }
+  }
+  return LiveIs;
+}
+
 bool LiveRegMatrix::checkRegMaskInterference(const LiveInterval &VirtReg,
                                              MCRegister PhysReg) {
   // Check if the cached information is valid.
@@ -178,7 +223,12 @@ bool LiveRegMatrix::checkRegUnitInterference(const LiveInterval &VirtReg,
   bool Result = foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
                                                        const LiveRange &Range) {
     const LiveRange &UnitRange = LIS->getRegUnit(Unit);
-    return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
+    LiveRange NewLR;
+    if (TRI->enableTargetInterference() &&
+        TRI->needUpdateECSlot(Range, NewLR = copyLiveRange(Range), *LIS))
+      return NewLR.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
+    else
+      return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
   });
   return Result;
 }
@@ -204,9 +254,24 @@ LiveRegMatrix::checkInterference(const LiveInterval &VirtReg,
   if (checkRegUnitInterference(VirtReg, PhysReg))
     return IK_RegUnit;
 
+  if (TRI->enableTargetInterference() &&
+      TRI->getTargetInterferenceReg(VirtReg, PhysReg, MRI, VRM).any())
+    return IK_VirtReg;
+
   // Check the matrix for virtual register interference.
   bool Interference = foreachUnit(TRI, VirtReg, PhysReg,
                                   [&](MCRegUnit Unit, const LiveRange &LR) {
+                                    LiveRange NewLR;
+                                    if (TRI->enableTargetInterference() &&
+                                        TRI->needUpdateECSlot(
+                                            LR, NewLR = copyLiveRange(LR), *LIS)) {
+                                      // Update LiveRange could make cache
+                                      // information stable. Refresh cache to
+                                      // handle it.
+                                      invalidateVirtRegs();
+                                      return query(NewLR, Unit)
+                                          .checkInterference();
+                                    } 
                                     return query(LR, Unit).checkInterference();
                                   });
   if (Interference)
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -921,6 +921,17 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
         // later.
         if (MO.isTied())
           ReadRegister(Reg, MI, RegularUse);
+        // If it be used by another instruction, it should not be deleted.Add commentMore actions
+        for (const MachineOperand &UseMO : MI.uses()) {
+          if (!UseMO.isReg())
+            continue;
+          MCRegister UseReg = UseMO.getReg().asMCReg();
+          if (UseReg == MCRegister::NoRegister)
+            continue;
+          if (!TRI->regsOverlap(Reg, UseReg))
+            continue;
+          ReadRegister(UseReg, MI, RegularUse);
+        }
         Tracker.clobberRegister(Reg, *TRI, *TII, UseCopyInstr);
       }
 
diff --git a/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp b/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
@@ -262,11 +262,15 @@ bool DefaultEvictionAdvisor::canEvictInterferenceBasedOnCost(
     LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
     // If there is 10 or more interferences, chances are one is heavier.
     const auto &Interferences = Q.interferingVRegs(EvictInterferenceCutoff);
-    if (Interferences.size() >= EvictInterferenceCutoff)
+    SmallVector<const LiveInterval *, 8> Intfs =
+        Matrix->getTargetInterferenceLiveI(VirtReg, PhysReg);
+    Intfs.append(Interferences.begin(), Interferences.end());
+
+    if (Intfs.size() >= EvictInterferenceCutoff)
       return false;
 
     // Check if any interfering live range is heavier than MaxWeight.
-    for (const LiveInterval *Intf : reverse(Interferences)) {
+    for (const LiveInterval *Intf : reverse(Intfs)) {
       assert(Intf->reg().isVirtual() &&
              "Only expecting virtual register interference from query");
 
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -635,6 +635,10 @@ void RAGreedy::evictInterference(const LiveInterval &VirtReg,
     Intfs.append(IVR.begin(), IVR.end());
   }
 
+  SmallVector<const LiveInterval *, 8> TargetIntfs =
+      Matrix->getTargetInterferenceLiveI(VirtReg, PhysReg);
+  Intfs.append(TargetIntfs.begin(), TargetIntfs.end());
+
   // Evict them second. This will invalidate the queries.
   for (const LiveInterval *Intf : Intfs) {
     // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2655,6 +2655,86 @@ void RISCVInstrInfo::genAlternativeCodeSequence(
   }
 }
 
+int RISCVInstrInfo::getOverlapConstraintsFromMI(uint16_t RVVPseudoOpcode) {
+  const RISCVVPseudosTable::PseudoInfo *RVV =
+      RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
+
+  if (!RVV)
+    return 0;
+
+  return RVV->TargetOverlapConstraintType;
+}
+
+static bool getConstrainsBetweenDstAndSrc(const MachineInstr *MBBI,
+                                          MachineOperand DestMO,
+                                          MachineOperand SrcMO,
+                                          int OverlapConstraintsType) {
+  MCRegister DestReg = DestMO.getReg();
+  MCRegister SrcReg = SrcMO.getReg();
+
+  unsigned DestRegIndex = RISCVRegisterInfo::getMCRegIndex(
+      DestReg, &MBBI->getParent()->getParent()->getRegInfo());
+  unsigned DestRegLMUL = RISCVRegisterInfo::getMCRegLMUL(DestReg);
+  unsigned SrcRegIndex = RISCVRegisterInfo::getMCRegIndex(
+      SrcReg, &MBBI->getParent()->getParent()->getRegInfo());
+  unsigned SrcRegLMUL = RISCVRegisterInfo::getMCRegLMUL(SrcReg);
+
+  if (OverlapConstraintsType == 2)
+    return RISCVRegisterInfo::isRVVConstraintsType2(DestRegIndex, DestRegLMUL,
+                                                    SrcRegIndex, SrcRegLMUL);
+  if (OverlapConstraintsType == 3)
+    return RISCVRegisterInfo::isRVVConstraintsType3(DestRegIndex, DestRegLMUL,
+                                                    SrcRegIndex, SrcRegLMUL);
+
+  return false;
+}
+
+// FIXME: Are we need support register like V26_V27?
+static bool isVectorPhyRegClass(MCRegister Reg) {
+  return (RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg) ||
+          RISCVMCRegisterClasses[RISCV::VRM2RegClassID].contains(Reg) ||
+          RISCVMCRegisterClasses[RISCV::VRM4RegClassID].contains(Reg) ||
+          RISCVMCRegisterClasses[RISCV::VRM8RegClassID].contains(Reg));
+}
+
+static bool getConstraintsWithDestAndAllSrc(const MachineInstr *MBBI,
+                                            int OverlapConstraintsType) {
+  bool NeedConstraint = false;
+  int DestOperand = 0; // assume Early-Clobber Operand is 0.
+
+  if (!MBBI->getOperand(DestOperand).isReg() ||
+      !MBBI->getOperand(DestOperand).getReg().isPhysical())
+    return false;
+
+  for (auto &MO : MBBI->uses()) {
+    if (!MO.isReg())
+      continue;
+    if (MO.isTied())
+      continue;
+    if (MO.getReg().isPhysical() && !MO.isImplicit() &&
+        isVectorPhyRegClass(MO.getReg()))
+      NeedConstraint |= getConstrainsBetweenDstAndSrc(
+          MBBI, MBBI->getOperand(DestOperand), MO, OverlapConstraintsType);
+  }
+
+  return NeedConstraint;
+}
+
+static bool hasTargetInterference(const MachineInstr *MBBI) {
+  int OverlapConstraintsType =
+      RISCVInstrInfo::getOverlapConstraintsFromMI(MBBI->getOpcode());
+  if (OverlapConstraintsType == 2 || OverlapConstraintsType == 3)
+    return getConstraintsWithDestAndAllSrc(MBBI, OverlapConstraintsType);
+
+  return false;
+}
+
+static bool isEarlyClobberMI(const MachineInstr *MBBI) {
+  return llvm::any_of(MBBI->defs(), [](const MachineOperand &DefMO) {
+    return DefMO.isReg() && DefMO.isEarlyClobber();
+  });
+}
+
 bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
                                        StringRef &ErrInfo) const {
   MCInstrDesc const &Desc = MI.getDesc();
@@ -2922,6 +3002,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
     return false;
   }
 
+  if (hasTargetInterference(&MI) && isEarlyClobberMI(&MI))
+    return false;
+
   return true;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -286,6 +286,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
   finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
                     SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
 
+  static int getOverlapConstraintsFromMI(uint16_t RVVPseudoOpcode);
+
   void genAlternativeCodeSequence(
       MachineInstr &Root, unsigned Pattern,
       SmallVectorImpl<MachineInstr *> &InsInstrs,
@@ -398,6 +400,7 @@ namespace RISCVVPseudosTable {
 struct PseudoInfo {
   uint16_t Pseudo;
   uint16_t BaseInstr;
+  uint16_t TargetOverlapConstraintType;
 };
 
 #define GET_RISCVVPseudosTable_DECL
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -556,6 +556,7 @@ defset list<VTypeInfoToWide> AllWidenableBFloatToFloatVectors = {
 class RISCVVPseudo {
   Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
   Instruction BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+  bits<2> TargetOverlapConstraintType = 1;
   // SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown).
   bits<8> SEW = 0;
   bit IncludeInInversePseudoTable = 1;
@@ -565,7 +566,7 @@ class RISCVVPseudo {
 def RISCVVPseudosTable : GenericTable {
   let FilterClass = "RISCVVPseudo";
   let CppTypeName = "PseudoInfo";
-  let Fields = [ "Pseudo", "BaseInstr" ];
+  let Fields = [ "Pseudo", "BaseInstr", "TargetOverlapConstraintType"];
   let PrimaryKey = [ "Pseudo" ];
   let PrimaryKeyName = "getPseudoInfo";
   let PrimaryKeyEarlyOut = true;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
