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Remove declarations
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‎llvm/test/CodeGen/RISCV/rvv/xandesvdot-vd4dots.ll‎

Lines changed: 0 additions & 117 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,6 @@
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvdot \
55
; RUN: -verify-machineinstrs -target-abi=lp64 | FileCheck %s
66

7-
declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8(
8-
<vscale x 1 x i32>,
9-
<vscale x 4 x i8>,
10-
<vscale x 4 x i8>,
11-
iXLen, iXLen);
12-
137
define <vscale x 1 x i32> @intrinsic_vd4dots_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {
148
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv1i32_nxv4i8_nxv4i8:
159
; CHECK: # %bb.0: # %entry
@@ -25,13 +19,6 @@ entry:
2519
ret <vscale x 1 x i32> %a
2620
}
2721

28-
declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.mask.nxv1i32.nxv4i8.nxv4i8(
29-
<vscale x 1 x i32>,
30-
<vscale x 4 x i8>,
31-
<vscale x 4 x i8>,
32-
<vscale x 1 x i1>,
33-
iXLen, iXLen);
34-
3522
define <vscale x 1 x i32> @intrinsic_vd4dots_mask_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1>%3, iXLen %4) nounwind {
3623
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv1i32_nxv4i8_nxv4i8:
3724
; CHECK: # %bb.0: # %entry
@@ -48,12 +35,6 @@ entry:
4835
ret <vscale x 1 x i32> %a
4936
}
5037

51-
declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8(
52-
<vscale x 2 x i32>,
53-
<vscale x 8 x i8>,
54-
<vscale x 8 x i8>,
55-
iXLen, iXLen);
56-
5738
define <vscale x 2 x i32> @intrinsic_vd4dots_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
5839
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv2i32_nxv8i8_nxv8i8:
5940
; CHECK: # %bb.0: # %entry
@@ -69,13 +50,6 @@ entry:
6950
ret <vscale x 2 x i32> %a
7051
}
7152

72-
declare <vscale x 2 x i32> @llvm.riscv.nds.vd4dots.mask.nxv2i32.nxv8i8.nxv8i8(
73-
<vscale x 2 x i32>,
74-
<vscale x 8 x i8>,
75-
<vscale x 8 x i8>,
76-
<vscale x 2 x i1>,
77-
iXLen, iXLen);
78-
7953
define <vscale x 2 x i32> @intrinsic_vd4dots_mask_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
8054
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv2i32_nxv8i8_nxv8i8:
8155
; CHECK: # %bb.0: # %entry
@@ -92,12 +66,6 @@ entry:
9266
ret <vscale x 2 x i32> %a
9367
}
9468

95-
declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8(
96-
<vscale x 4 x i32>,
97-
<vscale x 16 x i8>,
98-
<vscale x 16 x i8>,
99-
iXLen, iXLen);
100-
10169
define <vscale x 4 x i32> @intrinsic_vd4dots_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
10270
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv4i32_nxv16i8_nxv16i8:
10371
; CHECK: # %bb.0: # %entry
@@ -113,13 +81,6 @@ entry:
11381
ret <vscale x 4 x i32> %a
11482
}
11583

116-
declare <vscale x 4 x i32> @llvm.riscv.nds.vd4dots.mask.nxv4i32.nxv16i8.nxv16i8(
117-
<vscale x 4 x i32>,
118-
<vscale x 16 x i8>,
119-
<vscale x 16 x i8>,
120-
<vscale x 4 x i1>,
121-
iXLen, iXLen);
122-
12384
define <vscale x 4 x i32> @intrinsic_vd4dots_mask_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
12485
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv4i32_nxv16i8_nxv16i8:
12586
; CHECK: # %bb.0: # %entry
@@ -136,12 +97,6 @@ entry:
13697
ret <vscale x 4 x i32> %a
13798
}
13899

139-
declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8(
140-
<vscale x 8 x i32>,
141-
<vscale x 32 x i8>,
142-
<vscale x 32 x i8>,
143-
iXLen, iXLen);
144-
145100
define <vscale x 8 x i32> @intrinsic_vd4dots_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
146101
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv8i32_nxv32i8_nxv32i8:
147102
; CHECK: # %bb.0: # %entry
@@ -157,13 +112,6 @@ entry:
157112
ret <vscale x 8 x i32> %a
158113
}
159114

160-
declare <vscale x 8 x i32> @llvm.riscv.nds.vd4dots.mask.nxv8i32.nxv32i8.nxv32i8(
161-
<vscale x 8 x i32>,
162-
<vscale x 32 x i8>,
163-
<vscale x 32 x i8>,
164-
<vscale x 8 x i1>,
165-
iXLen, iXLen);
166-
167115
define <vscale x 8 x i32> @intrinsic_vd4dots_mask_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
168116
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv8i32_nxv32i8_nxv32i8:
169117
; CHECK: # %bb.0: # %entry
@@ -180,12 +128,6 @@ entry:
180128
ret <vscale x 8 x i32> %a
181129
}
182130

183-
declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8(
184-
<vscale x 16 x i32>,
185-
<vscale x 64 x i8>,
186-
<vscale x 64 x i8>,
187-
iXLen, iXLen);
188-
189131
define <vscale x 16 x i32> @intrinsic_vd4dots_vv_nxv16i32_nxv64i8_nxv64i8(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
190132
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv16i32_nxv64i8_nxv64i8:
191133
; CHECK: # %bb.0: # %entry
@@ -202,13 +144,6 @@ entry:
202144
ret <vscale x 16 x i32> %a
203145
}
204146

205-
declare <vscale x 16 x i32> @llvm.riscv.nds.vd4dots.mask.nxv16i32.nxv64i8.nxv64i8(
206-
<vscale x 16 x i32>,
207-
<vscale x 64 x i8>,
208-
<vscale x 64 x i8>,
209-
<vscale x 16 x i1>,
210-
iXLen, iXLen);
211-
212147
define <vscale x 16 x i32> @intrinsic_vd4dots_mask_vv_nxv16i32_nxv64i8_nxv64i8(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
213148
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv16i32_nxv64i8_nxv64i8:
214149
; CHECK: # %bb.0: # %entry
@@ -226,12 +161,6 @@ entry:
226161
ret <vscale x 16 x i32> %a
227162
}
228163

229-
declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16(
230-
<vscale x 1 x i64>,
231-
<vscale x 4 x i16>,
232-
<vscale x 4 x i16>,
233-
iXLen, iXLen);
234-
235164
define <vscale x 1 x i64> @intrinsic_vd4dots_vv_nxv1i64_nxv4i16_nxv4i16(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {
236165
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv1i64_nxv4i16_nxv4i16:
237166
; CHECK: # %bb.0: # %entry
@@ -247,13 +176,6 @@ entry:
247176
ret <vscale x 1 x i64> %a
248177
}
249178

250-
declare <vscale x 1 x i64> @llvm.riscv.nds.vd4dots.mask.nxv1i64.nxv4i16.nxv4i16(
251-
<vscale x 1 x i64>,
252-
<vscale x 4 x i16>,
253-
<vscale x 4 x i16>,
254-
<vscale x 1 x i1>,
255-
iXLen, iXLen);
256-
257179
define <vscale x 1 x i64> @intrinsic_vd4dots_mask_vv_nxv1i64_nxv4i16_nxv4i16(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
258180
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv1i64_nxv4i16_nxv4i16:
259181
; CHECK: # %bb.0: # %entry
@@ -270,12 +192,6 @@ entry:
270192
ret <vscale x 1 x i64> %a
271193
}
272194

273-
declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16(
274-
<vscale x 2 x i64>,
275-
<vscale x 8 x i16>,
276-
<vscale x 8 x i16>,
277-
iXLen, iXLen);
278-
279195
define <vscale x 2 x i64> @intrinsic_vd4dots_vv_nxv2i64_nxv8i16_nxv8i16(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {
280196
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv2i64_nxv8i16_nxv8i16:
281197
; CHECK: # %bb.0: # %entry
@@ -291,13 +207,6 @@ entry:
291207
ret <vscale x 2 x i64> %a
292208
}
293209

294-
declare <vscale x 2 x i64> @llvm.riscv.nds.vd4dots.mask.nxv2i64.nxv8i16.nxv8i16(
295-
<vscale x 2 x i64>,
296-
<vscale x 8 x i16>,
297-
<vscale x 8 x i16>,
298-
<vscale x 2 x i1>,
299-
iXLen, iXLen);
300-
301210
define <vscale x 2 x i64> @intrinsic_vd4dots_mask_vv_nxv2i64_nxv8i16_nxv8i16(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 2 x i1>%3, iXLen %4) nounwind {
302211
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv2i64_nxv8i16_nxv8i16:
303212
; CHECK: # %bb.0: # %entry
@@ -314,12 +223,6 @@ entry:
314223
ret <vscale x 2 x i64> %a
315224
}
316225

317-
declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16(
318-
<vscale x 4 x i64>,
319-
<vscale x 16 x i16>,
320-
<vscale x 16 x i16>,
321-
iXLen, iXLen);
322-
323226
define <vscale x 4 x i64> @intrinsic_vd4dots_vv_nxv4i64_nxv16i16_nxv16i16(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {
324227
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv4i64_nxv16i16_nxv16i16:
325228
; CHECK: # %bb.0: # %entry
@@ -335,13 +238,6 @@ entry:
335238
ret <vscale x 4 x i64> %a
336239
}
337240

338-
declare <vscale x 4 x i64> @llvm.riscv.nds.vd4dots.mask.nxv4i64.nxv16i16.nxv16i16(
339-
<vscale x 4 x i64>,
340-
<vscale x 16 x i16>,
341-
<vscale x 16 x i16>,
342-
<vscale x 4 x i1>,
343-
iXLen, iXLen);
344-
345241
define <vscale x 4 x i64> @intrinsic_vd4dots_mask_vv_nxv4i64_nxv16i16_nxv16i16(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
346242
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv4i64_nxv16i16_nxv16i16:
347243
; CHECK: # %bb.0: # %entry
@@ -358,12 +254,6 @@ entry:
358254
ret <vscale x 4 x i64> %a
359255
}
360256

361-
declare <vscale x 8 x i64> @llvm.riscv.nds.vd4dots.nxv8i64.nxv32i16.nxv32i16(
362-
<vscale x 8 x i64>,
363-
<vscale x 32 x i16>,
364-
<vscale x 32 x i16>,
365-
iXLen, iXLen);
366-
367257
define <vscale x 8 x i64> @intrinsic_vd4dots_vv_nxv8i64_nxv32i16_nxv32i16(<vscale x 8 x i64> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, iXLen %3) nounwind {
368258
; CHECK-LABEL: intrinsic_vd4dots_vv_nxv8i64_nxv32i16_nxv32i16:
369259
; CHECK: # %bb.0: # %entry
@@ -380,13 +270,6 @@ entry:
380270
ret <vscale x 8 x i64> %a
381271
}
382272

383-
declare <vscale x 8 x i64> @llvm.riscv.nds.vd4dots.mask.nxv8i64.nxv32i16.nxv32i16(
384-
<vscale x 8 x i64>,
385-
<vscale x 32 x i16>,
386-
<vscale x 32 x i16>,
387-
<vscale x 8 x i1>,
388-
iXLen, iXLen);
389-
390273
define <vscale x 8 x i64> @intrinsic_vd4dots_mask_vv_nxv8i64_nxv32i16_nxv32i16(<vscale x 8 x i64> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
391274
; CHECK-LABEL: intrinsic_vd4dots_mask_vv_nxv8i64_nxv32i16_nxv32i16:
392275
; CHECK: # %bb.0: # %entry

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