Skip to content

Commit 7f46c8e

Browse files
inbelicinbelic
committed
review: make stricter with check-next
1 parent bd36e8b commit 7f46c8e

File tree

2 files changed

+94
-88
lines changed

2 files changed

+94
-88
lines changed

‎llvm/test/CodeGen/DirectX/fshl.ll‎

Lines changed: 47 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,13 @@
77
; CHECK-SAME: i16 %[[A:.*]], i16 %[[B:.*]], i16 %[[SHIFT:.*]])
88
define noundef i16 @fshl_i16(i16 %a, i16 %b, i16 %shift) {
99
entry:
10-
; CHECK: %[[LEFT:.*]] = shl i16 %[[A]], %[[SHIFT]]
11-
; CHECK: %[[MASKED_SHIFT:.*]] = and i16 %[[SHIFT]], 15
12-
; CHECK: %[[INVERSE_SHIFT:.*]] = sub i16 16, %[[MASKED_SHIFT]]
13-
; CHECK: %[[RIGHT:.*]] = lshr i16 %[[B]], %[[INVERSE_SHIFT]]
14-
; CHECK: %[[RES:.*]] = or i16 %[[LEFT]], %[[RIGHT]]
15-
; CHECK: ret i16 %[[RES]]
10+
; CHECK-NEXT: entry:
11+
; CHECK-NEXT: %[[LEFT:.*]] = shl i16 %[[A]], %[[SHIFT]]
12+
; CHECK-NEXT: %[[MASKED_SHIFT:.*]] = and i16 %[[SHIFT]], 15
13+
; CHECK-NEXT: %[[INVERSE_SHIFT:.*]] = sub i16 16, %[[MASKED_SHIFT]]
14+
; CHECK-NEXT: %[[RIGHT:.*]] = lshr i16 %[[B]], %[[INVERSE_SHIFT]]
15+
; CHECK-NEXT: %[[RES:.*]] = or i16 %[[LEFT]], %[[RIGHT]]
16+
; CHECK-NEXT: ret i16 %[[RES]]
1617
%fsh = call i16 @llvm.fshl.i16(i16 %a, i16 %b, i16 %shift)
1718
ret i16 %fsh
1819
}
@@ -23,16 +24,17 @@ declare i16 @llvm.fshl.i16(i16, i16, i16)
2324
; CHECK-SAME: <1 x i32> %[[A_VEC:.*]], <1 x i32> %[[B_VEC:.*]], <1 x i32> %[[SHIFT_VEC:.*]])
2425
define noundef <1 x i32> @fshl_v1i32(<1 x i32> %a, <1 x i32> %b, <1 x i32> %shift) {
2526
entry:
26-
; CHECK: %[[A:.*]] = extractelement <1 x i32> %[[A_VEC]], i64 0
27-
; CHECK: %[[B:.*]] = extractelement <1 x i32> %[[B_VEC]], i64 0
28-
; CHECK: %[[SHIFT:.*]] = extractelement <1 x i32> %[[SHIFT_VEC]], i64 0
29-
; CHECK: %[[LEFT:.*]] = shl i32 %[[A]], %[[SHIFT]]
30-
; CHECK: %[[MASKED_SHIFT:.*]] = and i32 %[[SHIFT]], 31
31-
; CHECK: %[[INVERSE_SHIFT:.*]] = sub i32 32, %[[MASKED_SHIFT]]
32-
; CHECK: %[[RIGHT:.*]] = lshr i32 %[[B]], %[[INVERSE_SHIFT]]
33-
; CHECK: %[[RES:.*]] = or i32 %[[LEFT]], %[[RIGHT]]
34-
; CHECK: %[[RES_VEC:.*]] = insertelement <1 x i32> poison, i32 %[[RES]], i64 0
35-
; CHECK: ret <1 x i32> %[[RES_VEC]]
27+
; CHECK-NEXT: entry:
28+
; CHECK-NEXT: %[[A:.*]] = extractelement <1 x i32> %[[A_VEC]], i64 0
29+
; CHECK-NEXT: %[[B:.*]] = extractelement <1 x i32> %[[B_VEC]], i64 0
30+
; CHECK-NEXT: %[[SHIFT:.*]] = extractelement <1 x i32> %[[SHIFT_VEC]], i64 0
31+
; CHECK-NEXT: %[[LEFT:.*]] = shl i32 %[[A]], %[[SHIFT]]
32+
; CHECK-NEXT: %[[MASKED_SHIFT:.*]] = and i32 %[[SHIFT]], 31
33+
; CHECK-NEXT: %[[INVERSE_SHIFT:.*]] = sub i32 32, %[[MASKED_SHIFT]]
34+
; CHECK-NEXT: %[[RIGHT:.*]] = lshr i32 %[[B]], %[[INVERSE_SHIFT]]
35+
; CHECK-NEXT: %[[RES:.*]] = or i32 %[[LEFT]], %[[RIGHT]]
36+
; CHECK-NEXT: %[[RES_VEC:.*]] = insertelement <1 x i32> poison, i32 %[[RES]], i64 0
37+
; CHECK-NEXT: ret <1 x i32> %[[RES_VEC]]
3638
%fsh = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %b, <1 x i32> %shift)
3739
ret <1 x i32> %fsh
3840
}
@@ -43,38 +45,39 @@ declare <1 x i32> @llvm.fshl.v1i32(<1 x i32>, <1 x i32>, <1 x i32>)
4345
; CHECK-SAME: <3 x i64> %[[A_VEC:.*]], <3 x i64> %[[B_VEC:.*]], <3 x i64> %[[SHIFT_VEC:.*]])
4446
define noundef <3 x i64> @fshl_v1i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %shift) {
4547
entry:
46-
; CHECK: %[[A0:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 0
47-
; CHECK: %[[B0:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 0
48-
; CHECK: %[[SHIFT0:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 0
49-
; CHECK: %[[LEFT0:.*]] = shl i64 %[[A0]], %[[SHIFT0]]
50-
; CHECK: %[[MASKED_SHIFT0:.*]] = and i64 %[[SHIFT0]], 63
51-
; CHECK: %[[INVERSE_SHIFT0:.*]] = sub i64 64, %[[MASKED_SHIFT0]]
52-
; CHECK: %[[RIGHT0:.*]] = lshr i64 %[[B0]], %[[INVERSE_SHIFT0]]
53-
; CHECK: %[[RES0:.*]] = or i64 %[[LEFT0]], %[[RIGHT0]]
48+
; CHECK-NEXT: entry:
49+
; CHECK-NEXT: %[[A0:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 0
50+
; CHECK-NEXT: %[[B0:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 0
51+
; CHECK-NEXT: %[[SHIFT0:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 0
52+
; CHECK-NEXT: %[[LEFT0:.*]] = shl i64 %[[A0]], %[[SHIFT0]]
53+
; CHECK-NEXT: %[[MASKED_SHIFT0:.*]] = and i64 %[[SHIFT0]], 63
54+
; CHECK-NEXT: %[[INVERSE_SHIFT0:.*]] = sub i64 64, %[[MASKED_SHIFT0]]
55+
; CHECK-NEXT: %[[RIGHT0:.*]] = lshr i64 %[[B0]], %[[INVERSE_SHIFT0]]
56+
; CHECK-NEXT: %[[RES0:.*]] = or i64 %[[LEFT0]], %[[RIGHT0]]
5457
;
55-
; CHECK: %[[A1:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 1
56-
; CHECK: %[[B1:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 1
57-
; CHECK: %[[SHIFT1:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 1
58-
; CHECK: %[[LEFT1:.*]] = shl i64 %[[A1]], %[[SHIFT1]]
59-
; CHECK: %[[MASKED_SHIFT1:.*]] = and i64 %[[SHIFT1]], 63
60-
; CHECK: %[[INVERSE_SHIFT1:.*]] = sub i64 64, %[[MASKED_SHIFT1]]
61-
; CHECK: %[[RIGHT1:.*]] = lshr i64 %[[B1]], %[[INVERSE_SHIFT1]]
62-
; CHECK: %[[RES1:.*]] = or i64 %[[LEFT1]], %[[RIGHT1]]
58+
; CHECK-NEXT: %[[A1:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 1
59+
; CHECK-NEXT: %[[B1:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 1
60+
; CHECK-NEXT: %[[SHIFT1:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 1
61+
; CHECK-NEXT: %[[LEFT1:.*]] = shl i64 %[[A1]], %[[SHIFT1]]
62+
; CHECK-NEXT: %[[MASKED_SHIFT1:.*]] = and i64 %[[SHIFT1]], 63
63+
; CHECK-NEXT: %[[INVERSE_SHIFT1:.*]] = sub i64 64, %[[MASKED_SHIFT1]]
64+
; CHECK-NEXT: %[[RIGHT1:.*]] = lshr i64 %[[B1]], %[[INVERSE_SHIFT1]]
65+
; CHECK-NEXT: %[[RES1:.*]] = or i64 %[[LEFT1]], %[[RIGHT1]]
6366
;
64-
; CHECK: %[[A2:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 2
65-
; CHECK: %[[B2:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 2
66-
; CHECK: %[[SHIFT2:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 2
67-
; CHECK: %[[LEFT2:.*]] = shl i64 %[[A2]], %[[SHIFT2]]
68-
; CHECK: %[[MASKED_SHIFT2:.*]] = and i64 %[[SHIFT2]], 63
69-
; CHECK: %[[INVERSE_SHIFT2:.*]] = sub i64 64, %[[MASKED_SHIFT2]]
70-
; CHECK: %[[RIGHT2:.*]] = lshr i64 %[[B2]], %[[INVERSE_SHIFT2]]
71-
; CHECK: %[[RES2:.*]] = or i64 %[[LEFT2]], %[[RIGHT2]]
67+
; CHECK-NEXT: %[[A2:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 2
68+
; CHECK-NEXT: %[[B2:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 2
69+
; CHECK-NEXT: %[[SHIFT2:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 2
70+
; CHECK-NEXT: %[[LEFT2:.*]] = shl i64 %[[A2]], %[[SHIFT2]]
71+
; CHECK-NEXT: %[[MASKED_SHIFT2:.*]] = and i64 %[[SHIFT2]], 63
72+
; CHECK-NEXT: %[[INVERSE_SHIFT2:.*]] = sub i64 64, %[[MASKED_SHIFT2]]
73+
; CHECK-NEXT: %[[RIGHT2:.*]] = lshr i64 %[[B2]], %[[INVERSE_SHIFT2]]
74+
; CHECK-NEXT: %[[RES2:.*]] = or i64 %[[LEFT2]], %[[RIGHT2]]
7275
;
73-
; CHECK: %[[INSERT0:.*]] = insertelement <3 x i64> poison, i64 %[[RES0]], i64 0
74-
; CHECK: %[[INSERT1:.*]] = insertelement <3 x i64> %[[INSERT0]], i64 %[[RES1]], i64 1
75-
; CHECK: %[[RES_VEC:.*]] = insertelement <3 x i64> %[[INSERT1]], i64 %[[RES2]], i64 2
76+
; CHECK-NEXT: %[[INSERT0:.*]] = insertelement <3 x i64> poison, i64 %[[RES0]], i64 0
77+
; CHECK-NEXT: %[[INSERT1:.*]] = insertelement <3 x i64> %[[INSERT0]], i64 %[[RES1]], i64 1
78+
; CHECK-NEXT: %[[RES_VEC:.*]] = insertelement <3 x i64> %[[INSERT1]], i64 %[[RES2]], i64 2
7679
;
77-
; CHECK: ret <3 x i64> %[[RES_VEC]]
80+
; CHECK-NEXT: ret <3 x i64> %[[RES_VEC]]
7881
%fsh = call <3 x i64> @llvm.fshl.v1i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %shift)
7982
ret <3 x i64> %fsh
8083
}

‎llvm/test/CodeGen/DirectX/fshr.ll‎

Lines changed: 47 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,13 @@
77
; CHECK-SAME: i16 %[[A:.*]], i16 %[[B:.*]], i16 %[[SHIFT:.*]])
88
define noundef i16 @fshr_i16(i16 %a, i16 %b, i16 %shift) {
99
entry:
10-
; CHECK: %[[LEFT:.*]] = lshr i16 %[[B]], %[[SHIFT]]
11-
; CHECK: %[[MASKED_SHIFT:.*]] = and i16 %[[SHIFT]], 15
12-
; CHECK: %[[INVERSE_SHIFT:.*]] = sub i16 16, %[[MASKED_SHIFT]]
13-
; CHECK: %[[RIGHT:.*]] = shl i16 %[[A]], %[[INVERSE_SHIFT]]
14-
; CHECK: %[[RES:.*]] = or i16 %[[LEFT]], %[[RIGHT]]
15-
; CHECK: ret i16 %[[RES]]
10+
; CHECK-NEXT: entry:
11+
; CHECK-NEXT: %[[LEFT:.*]] = lshr i16 %[[B]], %[[SHIFT]]
12+
; CHECK-NEXT: %[[MASKED_SHIFT:.*]] = and i16 %[[SHIFT]], 15
13+
; CHECK-NEXT: %[[INVERSE_SHIFT:.*]] = sub i16 16, %[[MASKED_SHIFT]]
14+
; CHECK-NEXT: %[[RIGHT:.*]] = shl i16 %[[A]], %[[INVERSE_SHIFT]]
15+
; CHECK-NEXT: %[[RES:.*]] = or i16 %[[LEFT]], %[[RIGHT]]
16+
; CHECK-NEXT: ret i16 %[[RES]]
1617
%fsh = call i16 @llvm.fshr.i16(i16 %a, i16 %b, i16 %shift)
1718
ret i16 %fsh
1819
}
@@ -23,16 +24,17 @@ declare i16 @llvm.fshr.i16(i16, i16, i16)
2324
; CHECK-SAME: <1 x i32> %[[A_VEC:.*]], <1 x i32> %[[B_VEC:.*]], <1 x i32> %[[SHIFT_VEC:.*]])
2425
define noundef <1 x i32> @fshr_v1i32(<1 x i32> %a, <1 x i32> %b, <1 x i32> %shift) {
2526
entry:
26-
; CHECK: %[[A:.*]] = extractelement <1 x i32> %[[A_VEC]], i64 0
27-
; CHECK: %[[B:.*]] = extractelement <1 x i32> %[[B_VEC]], i64 0
28-
; CHECK: %[[SHIFT:.*]] = extractelement <1 x i32> %[[SHIFT_VEC]], i64 0
29-
; CHECK: %[[LEFT:.*]] = lshr i32 %[[B]], %[[SHIFT]]
30-
; CHECK: %[[MASKED_SHIFT:.*]] = and i32 %[[SHIFT]], 31
31-
; CHECK: %[[INVERSE_SHIFT:.*]] = sub i32 32, %[[MASKED_SHIFT]]
32-
; CHECK: %[[RIGHT:.*]] = shl i32 %[[A]], %[[INVERSE_SHIFT]]
33-
; CHECK: %[[RES:.*]] = or i32 %[[LEFT]], %[[RIGHT]]
34-
; CHECK: %[[RES_VEC:.*]] = insertelement <1 x i32> poison, i32 %[[RES]], i64 0
35-
; CHECK: ret <1 x i32> %[[RES_VEC]]
27+
; CHECK-NEXT: entry:
28+
; CHECK-NEXT: %[[A:.*]] = extractelement <1 x i32> %[[A_VEC]], i64 0
29+
; CHECK-NEXT: %[[B:.*]] = extractelement <1 x i32> %[[B_VEC]], i64 0
30+
; CHECK-NEXT: %[[SHIFT:.*]] = extractelement <1 x i32> %[[SHIFT_VEC]], i64 0
31+
; CHECK-NEXT: %[[LEFT:.*]] = lshr i32 %[[B]], %[[SHIFT]]
32+
; CHECK-NEXT: %[[MASKED_SHIFT:.*]] = and i32 %[[SHIFT]], 31
33+
; CHECK-NEXT: %[[INVERSE_SHIFT:.*]] = sub i32 32, %[[MASKED_SHIFT]]
34+
; CHECK-NEXT: %[[RIGHT:.*]] = shl i32 %[[A]], %[[INVERSE_SHIFT]]
35+
; CHECK-NEXT: %[[RES:.*]] = or i32 %[[LEFT]], %[[RIGHT]]
36+
; CHECK-NEXT: %[[RES_VEC:.*]] = insertelement <1 x i32> poison, i32 %[[RES]], i64 0
37+
; CHECK-NEXT: ret <1 x i32> %[[RES_VEC]]
3638
%fsh = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %b, <1 x i32> %shift)
3739
ret <1 x i32> %fsh
3840
}
@@ -43,38 +45,39 @@ declare <1 x i32> @llvm.fshr.v1i32(<1 x i32>, <1 x i32>, <1 x i32>)
4345
; CHECK-SAME: <3 x i64> %[[A_VEC:.*]], <3 x i64> %[[B_VEC:.*]], <3 x i64> %[[SHIFT_VEC:.*]])
4446
define noundef <3 x i64> @fshr_v1i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %shift) {
4547
entry:
46-
; CHECK: %[[A0:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 0
47-
; CHECK: %[[B0:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 0
48-
; CHECK: %[[SHIFT0:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 0
49-
; CHECK: %[[LEFT0:.*]] = lshr i64 %[[B0]], %[[SHIFT0]]
50-
; CHECK: %[[MASKED_SHIFT0:.*]] = and i64 %[[SHIFT0]], 63
51-
; CHECK: %[[INVERSE_SHIFT0:.*]] = sub i64 64, %[[MASKED_SHIFT0]]
52-
; CHECK: %[[RIGHT0:.*]] = shl i64 %[[A0]], %[[INVERSE_SHIFT0]]
53-
; CHECK: %[[RES0:.*]] = or i64 %[[LEFT0]], %[[RIGHT0]]
48+
; CHECK-NEXT: entry:
49+
; CHECK-NEXT: %[[A0:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 0
50+
; CHECK-NEXT: %[[B0:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 0
51+
; CHECK-NEXT: %[[SHIFT0:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 0
52+
; CHECK-NEXT: %[[LEFT0:.*]] = lshr i64 %[[B0]], %[[SHIFT0]]
53+
; CHECK-NEXT: %[[MASKED_SHIFT0:.*]] = and i64 %[[SHIFT0]], 63
54+
; CHECK-NEXT: %[[INVERSE_SHIFT0:.*]] = sub i64 64, %[[MASKED_SHIFT0]]
55+
; CHECK-NEXT: %[[RIGHT0:.*]] = shl i64 %[[A0]], %[[INVERSE_SHIFT0]]
56+
; CHECK-NEXT: %[[RES0:.*]] = or i64 %[[LEFT0]], %[[RIGHT0]]
5457
;
55-
; CHECK: %[[A1:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 1
56-
; CHECK: %[[B1:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 1
57-
; CHECK: %[[SHIFT1:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 1
58-
; CHECK: %[[LEFT1:.*]] = lshr i64 %[[B1]], %[[SHIFT1]]
59-
; CHECK: %[[MASKED_SHIFT1:.*]] = and i64 %[[SHIFT1]], 63
60-
; CHECK: %[[INVERSE_SHIFT1:.*]] = sub i64 64, %[[MASKED_SHIFT1]]
61-
; CHECK: %[[RIGHT1:.*]] = shl i64 %[[A1]], %[[INVERSE_SHIFT1]]
62-
; CHECK: %[[RES1:.*]] = or i64 %[[LEFT1]], %[[RIGHT1]]
58+
; CHECK-NEXT: %[[A1:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 1
59+
; CHECK-NEXT: %[[B1:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 1
60+
; CHECK-NEXT: %[[SHIFT1:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 1
61+
; CHECK-NEXT: %[[LEFT1:.*]] = lshr i64 %[[B1]], %[[SHIFT1]]
62+
; CHECK-NEXT: %[[MASKED_SHIFT1:.*]] = and i64 %[[SHIFT1]], 63
63+
; CHECK-NEXT: %[[INVERSE_SHIFT1:.*]] = sub i64 64, %[[MASKED_SHIFT1]]
64+
; CHECK-NEXT: %[[RIGHT1:.*]] = shl i64 %[[A1]], %[[INVERSE_SHIFT1]]
65+
; CHECK-NEXT: %[[RES1:.*]] = or i64 %[[LEFT1]], %[[RIGHT1]]
6366
;
64-
; CHECK: %[[A2:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 2
65-
; CHECK: %[[B2:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 2
66-
; CHECK: %[[SHIFT2:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 2
67-
; CHECK: %[[LEFT2:.*]] = lshr i64 %[[B2]], %[[SHIFT2]]
68-
; CHECK: %[[MASKED_SHIFT2:.*]] = and i64 %[[SHIFT2]], 63
69-
; CHECK: %[[INVERSE_SHIFT2:.*]] = sub i64 64, %[[MASKED_SHIFT2]]
70-
; CHECK: %[[RIGHT2:.*]] = shl i64 %[[A2]], %[[INVERSE_SHIFT2]]
71-
; CHECK: %[[RES2:.*]] = or i64 %[[LEFT2]], %[[RIGHT2]]
67+
; CHECK-NEXT: %[[A2:.*]] = extractelement <3 x i64> %[[A_VEC]], i64 2
68+
; CHECK-NEXT: %[[B2:.*]] = extractelement <3 x i64> %[[B_VEC]], i64 2
69+
; CHECK-NEXT: %[[SHIFT2:.*]] = extractelement <3 x i64> %[[SHIFT_VEC]], i64 2
70+
; CHECK-NEXT: %[[LEFT2:.*]] = lshr i64 %[[B2]], %[[SHIFT2]]
71+
; CHECK-NEXT: %[[MASKED_SHIFT2:.*]] = and i64 %[[SHIFT2]], 63
72+
; CHECK-NEXT: %[[INVERSE_SHIFT2:.*]] = sub i64 64, %[[MASKED_SHIFT2]]
73+
; CHECK-NEXT: %[[RIGHT2:.*]] = shl i64 %[[A2]], %[[INVERSE_SHIFT2]]
74+
; CHECK-NEXT: %[[RES2:.*]] = or i64 %[[LEFT2]], %[[RIGHT2]]
7275
;
73-
; CHECK: %[[INSERT0:.*]] = insertelement <3 x i64> poison, i64 %[[RES0]], i64 0
74-
; CHECK: %[[INSERT1:.*]] = insertelement <3 x i64> %[[INSERT0]], i64 %[[RES1]], i64 1
75-
; CHECK: %[[RES_VEC:.*]] = insertelement <3 x i64> %[[INSERT1]], i64 %[[RES2]], i64 2
76+
; CHECK-NEXT: %[[INSERT0:.*]] = insertelement <3 x i64> poison, i64 %[[RES0]], i64 0
77+
; CHECK-NEXT: %[[INSERT1:.*]] = insertelement <3 x i64> %[[INSERT0]], i64 %[[RES1]], i64 1
78+
; CHECK-NEXT: %[[RES_VEC:.*]] = insertelement <3 x i64> %[[INSERT1]], i64 %[[RES2]], i64 2
7679
;
77-
; CHECK: ret <3 x i64> %[[RES_VEC]]
80+
; CHECK-NEXT: ret <3 x i64> %[[RES_VEC]]
7881
%fsh = call <3 x i64> @llvm.fshr.v1i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %shift)
7982
ret <3 x i64> %fsh
8083
}

0 commit comments

Comments
 (0)