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rebase. update codegen test
Created using spr 1.3.5-bogner
2 parents a7f6b41 + 2bfc488 commit 7f477b9

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43 files changed

+918
-882
lines changed

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,8 @@ namespace {
3131

3232
class AArch64AsmBackend : public MCAsmBackend {
3333
static const unsigned PCRelFlagVal =
34-
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
34+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits;
35+
3536
protected:
3637
Triple TheTriple;
3738

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp‎

Lines changed: 18 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,11 @@ class AArch64MCCodeEmitter : public MCCodeEmitter {
223223

224224
} // end anonymous namespace
225225

226+
static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
227+
const MCExpr *Value, uint16_t Kind, bool PCRel = false) {
228+
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
229+
}
230+
226231
/// getMachineOpValue - Return binary encoding of operand. If the machine
227232
/// operand requires relocation, record the relocation and return zero.
228233
unsigned
@@ -248,7 +253,7 @@ AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
248253
else {
249254
assert(MO.isExpr() && "unable to encode load/store imm operand");
250255
MCFixupKind Kind = MCFixupKind(FixupKind);
251-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
256+
addFixup(Fixups, 0, MO.getExpr(), Kind);
252257
++MCNumFixups;
253258
}
254259

@@ -272,7 +277,7 @@ AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
272277
unsigned Kind = MI.getOpcode() == AArch64::ADR
273278
? AArch64::fixup_aarch64_pcrel_adr_imm21
274279
: AArch64::fixup_aarch64_pcrel_adrp_imm21;
275-
Fixups.push_back(MCFixup::create(0, Expr, Kind, true));
280+
addFixup(Fixups, 0, Expr, Kind, true);
276281
MCNumFixups += 1;
277282
return 0;
278283
}
@@ -299,7 +304,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
299304

300305
// Encode the 12 bits of the fixup.
301306
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
302-
Fixups.push_back(MCFixup::create(0, Expr, Kind));
307+
addFixup(Fixups, 0, Expr, Kind);
303308

304309
++MCNumFixups;
305310

@@ -326,8 +331,8 @@ uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
326331
return MO.getImm();
327332
assert(MO.isExpr() && "Unexpected target type!");
328333

329-
Fixups.push_back(MCFixup::create(
330-
0, MO.getExpr(), AArch64::fixup_aarch64_pcrel_branch19, true));
334+
addFixup(Fixups, 0, MO.getExpr(), AArch64::fixup_aarch64_pcrel_branch19,
335+
true);
331336
++MCNumFixups;
332337
return 0;
333338
}
@@ -364,8 +369,8 @@ AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
364369
return -(MO.getImm());
365370
assert(MO.isExpr() && "Unexpected target type!");
366371

367-
Fixups.push_back(MCFixup::create(
368-
0, MO.getExpr(), AArch64::fixup_aarch64_pcrel_branch16, true));
372+
addFixup(Fixups, 0, MO.getExpr(), AArch64::fixup_aarch64_pcrel_branch16,
373+
true);
369374
++MCNumFixups;
370375
return 0;
371376
}
@@ -383,8 +388,8 @@ AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
383388
return MO.getImm();
384389
assert(MO.isExpr() && "Unexpected target type!");
385390

386-
Fixups.push_back(MCFixup::create(
387-
0, MO.getExpr(), AArch64::fixup_aarch64_ldr_pcrel_imm19, true));
391+
addFixup(Fixups, 0, MO.getExpr(), AArch64::fixup_aarch64_ldr_pcrel_imm19,
392+
true);
388393
++MCNumFixups;
389394
return 0;
390395
}
@@ -428,8 +433,8 @@ uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
428433
return MO.getImm();
429434
assert(MO.isExpr() && "Unexpected ADR target type!");
430435

431-
Fixups.push_back(MCFixup::create(
432-
0, MO.getExpr(), AArch64::fixup_aarch64_pcrel_branch14, true));
436+
addFixup(Fixups, 0, MO.getExpr(), AArch64::fixup_aarch64_pcrel_branch14,
437+
true);
433438
++MCNumFixups;
434439
return 0;
435440
}
@@ -450,7 +455,7 @@ AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
450455
unsigned Kind = MI.getOpcode() == AArch64::BL
451456
? AArch64::fixup_aarch64_pcrel_call26
452457
: AArch64::fixup_aarch64_pcrel_branch26;
453-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, true));
458+
addFixup(Fixups, 0, MO.getExpr(), Kind, true);
454459

455460
++MCNumFixups;
456461

@@ -730,7 +735,7 @@ void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI,
730735
auto Reloc = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32
731736
? ELF::R_AARCH64_P32_TLSDESC_CALL
732737
: ELF::R_AARCH64_TLSDESC_CALL;
733-
Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Reloc));
738+
addFixup(Fixups, 0, MI.getOperand(0).getExpr(), Reloc);
734739
return;
735740
}
736741

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,9 @@ MCFixupKindInfo LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
5757
// LoongArchFixupKinds.h.
5858
//
5959
// {name, offset, bits, flags}
60-
{"fixup_loongarch_b16", 10, 16, MCFixupKindInfo::FKF_IsPCRel},
61-
{"fixup_loongarch_b21", 0, 26, MCFixupKindInfo::FKF_IsPCRel},
62-
{"fixup_loongarch_b26", 0, 26, MCFixupKindInfo::FKF_IsPCRel},
60+
{"fixup_loongarch_b16", 10, 16, 0},
61+
{"fixup_loongarch_b21", 0, 26, 0},
62+
{"fixup_loongarch_b26", 0, 26, 0},
6363
{"fixup_loongarch_abs_hi20", 5, 20, 0},
6464
{"fixup_loongarch_abs_lo12", 10, 12, 0},
6565
{"fixup_loongarch_abs64_lo20", 5, 20, 0},

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp‎

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,18 @@ class LoongArchMCCodeEmitter : public MCCodeEmitter {
9797
};
9898
} // end namespace
9999

100+
static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
101+
const MCExpr *Value, uint16_t Kind) {
102+
bool PCRel = false;
103+
switch (Kind) {
104+
case LoongArch::fixup_loongarch_b16:
105+
case LoongArch::fixup_loongarch_b21:
106+
case LoongArch::fixup_loongarch_b26:
107+
PCRel = true;
108+
}
109+
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
110+
}
111+
100112
unsigned
101113
LoongArchMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
102114
SmallVectorImpl<MCFixup> &Fixups,
@@ -195,7 +207,7 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
195207
assert(FixupKind != LoongArch::fixup_loongarch_invalid &&
196208
"Unhandled expression!");
197209

198-
Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
210+
addFixup(Fixups, 0, Expr, FixupKind);
199211
// If linker relaxation is enabled and supported by this relocation, set
200212
// a bit so that if fixup is unresolved, a R_LARCH_RELAX relocation will be
201213
// appended.
@@ -248,7 +260,7 @@ void LoongArchMCCodeEmitter::expandAddTPRel(const MCInst &MI,
248260
"Expected %le_add_r relocation on TP-relative symbol");
249261

250262
// Emit the correct %le_add_r relocation for the symbol.
251-
Fixups.push_back(MCFixup::create(0, Expr, ELF::R_LARCH_TLS_LE_ADD_R));
263+
addFixup(Fixups, 0, Expr, ELF::R_LARCH_TLS_LE_ADD_R);
252264
if (STI.hasFeature(LoongArch::FeatureRelax))
253265
Fixups.back().setLinkerRelaxable();
254266

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -69,23 +69,23 @@ MCFixupKindInfo RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
6969
{"fixup_riscv_lo12_i", 20, 12, 0},
7070
{"fixup_riscv_12_i", 20, 12, 0},
7171
{"fixup_riscv_lo12_s", 0, 32, 0},
72-
{"fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
73-
{"fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsPCRel},
74-
{"fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
75-
{"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
76-
{"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
77-
{"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
78-
{"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
79-
{"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
80-
{"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
81-
82-
{"fixup_riscv_qc_e_branch", 0, 48, MCFixupKindInfo::FKF_IsPCRel},
72+
{"fixup_riscv_pcrel_hi20", 12, 20, 0},
73+
{"fixup_riscv_pcrel_lo12_i", 20, 12, 0},
74+
{"fixup_riscv_pcrel_lo12_s", 0, 32, 0},
75+
{"fixup_riscv_jal", 12, 20, 0},
76+
{"fixup_riscv_branch", 0, 32, 0},
77+
{"fixup_riscv_rvc_jump", 2, 11, 0},
78+
{"fixup_riscv_rvc_branch", 0, 16, 0},
79+
{"fixup_riscv_call", 0, 64, 0},
80+
{"fixup_riscv_call_plt", 0, 64, 0},
81+
82+
{"fixup_riscv_qc_e_branch", 0, 48, 0},
8383
{"fixup_riscv_qc_e_32", 16, 32, 0},
8484
{"fixup_riscv_qc_abs20_u", 12, 20, 0},
85-
{"fixup_riscv_qc_e_call_plt", 0, 48, MCFixupKindInfo::FKF_IsPCRel},
85+
{"fixup_riscv_qc_e_call_plt", 0, 48, 0},
8686

8787
// Andes fixups
88-
{"fixup_riscv_nds_branch_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
88+
{"fixup_riscv_nds_branch_10", 0, 32, 0},
8989
};
9090
static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
9191
"Not all fixup kinds added to Infos array");

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp‎

Lines changed: 29 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,28 @@ MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
120120
return new RISCVMCCodeEmitter(Ctx, MCII);
121121
}
122122

123+
static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
124+
const MCExpr *Value, uint16_t Kind) {
125+
bool PCRel = false;
126+
switch (Kind) {
127+
case ELF::R_RISCV_CALL_PLT:
128+
case RISCV::fixup_riscv_pcrel_hi20:
129+
case RISCV::fixup_riscv_pcrel_lo12_i:
130+
case RISCV::fixup_riscv_pcrel_lo12_s:
131+
case RISCV::fixup_riscv_jal:
132+
case RISCV::fixup_riscv_branch:
133+
case RISCV::fixup_riscv_rvc_jump:
134+
case RISCV::fixup_riscv_rvc_branch:
135+
case RISCV::fixup_riscv_call:
136+
case RISCV::fixup_riscv_call_plt:
137+
case RISCV::fixup_riscv_qc_e_branch:
138+
case RISCV::fixup_riscv_qc_e_call_plt:
139+
case RISCV::fixup_riscv_nds_branch_10:
140+
PCRel = true;
141+
}
142+
Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
143+
}
144+
123145
// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
124146
// relocation types. We expand those pseudo-instructions while encoding them,
125147
// meaning AUIPC and JALR won't go through RISC-V MC to MC compressed
@@ -181,7 +203,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
181203
MCRegister Link = MI.getOperand(0).getReg();
182204
MCRegister Dest = MI.getOperand(1).getReg();
183205
int64_t Imm = MI.getOperand(2).getImm();
184-
Fixups.push_back(MCFixup::create(0, Expr, ELF::R_RISCV_TLSDESC_CALL));
206+
addFixup(Fixups, 0, Expr, ELF::R_RISCV_TLSDESC_CALL);
185207
MCInst Call =
186208
MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
187209

@@ -208,7 +230,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
208230
assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
209231
"Expected tprel_add relocation on TP-relative symbol");
210232

211-
Fixups.push_back(MCFixup::create(0, Expr, ELF::R_RISCV_TPREL_ADD));
233+
addFixup(Fixups, 0, Expr, ELF::R_RISCV_TPREL_ADD);
212234
if (STI.hasFeature(RISCV::FeatureRelax))
213235
Fixups.back().setLinkerRelaxable();
214236

@@ -318,10 +340,8 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
318340
// Drop any fixup added so we can add the correct one.
319341
Fixups.resize(FixupStartIndex);
320342

321-
if (SrcSymbol.isExpr()) {
322-
Fixups.push_back(
323-
MCFixup::create(Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal));
324-
}
343+
if (SrcSymbol.isExpr())
344+
addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
325345
}
326346

327347
// Expand PseudoLongQC_(E_)Bxxx to an inverted conditional branch and an
@@ -368,10 +388,8 @@ void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI,
368388
support::endian::write(CB, JBinary, llvm::endianness::little);
369389
// Drop any fixup added so we can add the correct one.
370390
Fixups.resize(FixupStartIndex);
371-
if (SrcSymbol.isExpr()) {
372-
Fixups.push_back(
373-
MCFixup::create(Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal));
374-
}
391+
if (SrcSymbol.isExpr())
392+
addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
375393
}
376394

377395
void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,
@@ -649,7 +667,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
649667

650668
assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
651669

652-
Fixups.push_back(MCFixup::create(0, Expr, FixupKind));
670+
addFixup(Fixups, 0, Expr, FixupKind);
653671
// If linker relaxation is enabled and supported by this relocation, set
654672
// a bit so that if fixup is unresolved, a R_RISCV_RELAX relocation will be
655673
// appended.

‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -624,17 +624,17 @@ std::optional<MCFixupKind> X86AsmBackend::getFixupKind(StringRef Name) const {
624624
MCFixupKindInfo X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
625625
const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
626626
// clang-format off
627-
{"reloc_riprel_4byte", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
628-
{"reloc_riprel_4byte_movq_load", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
629-
{"reloc_riprel_4byte_movq_load_rex2", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
630-
{"reloc_riprel_4byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
631-
{"reloc_riprel_4byte_relax_rex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
632-
{"reloc_riprel_4byte_relax_rex2", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
633-
{"reloc_riprel_4byte_relax_evex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
627+
{"reloc_riprel_4byte", 0, 32, 0},
628+
{"reloc_riprel_4byte_movq_load", 0, 32, 0},
629+
{"reloc_riprel_4byte_movq_load_rex2", 0, 32, 0},
630+
{"reloc_riprel_4byte_relax", 0, 32, 0},
631+
{"reloc_riprel_4byte_relax_rex", 0, 32, 0},
632+
{"reloc_riprel_4byte_relax_rex2", 0, 32, 0},
633+
{"reloc_riprel_4byte_relax_evex", 0, 32, 0},
634634
{"reloc_signed_4byte", 0, 32, 0},
635635
{"reloc_signed_4byte_relax", 0, 32, 0},
636636
{"reloc_global_offset_table", 0, 32, 0},
637-
{"reloc_branch_4byte_pcrel", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
637+
{"reloc_branch_4byte_pcrel", 0, 32, 0},
638638
// clang-format on
639639
};
640640

‎llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ define dso_local void @test1(ptr%buf) nounwind {
8787
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
8888
; EGPR-NEXT: testb %al, %al # encoding: [0x84,0xc0]
8989
; EGPR-NEXT: jne .LBB0_3 # encoding: [0x75,A]
90-
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB0_3-1, kind: FK_PCRel_1
90+
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB0_3, kind: FK_PCRel_1
9191
; EGPR-NEXT: # %bb.1: # %loop.header.preheader
9292
; EGPR-NEXT: movq %rdi, %rbx # encoding: [0x48,0x89,0xfb]
9393
; EGPR-NEXT: xorl %r14d, %r14d # encoding: [0x45,0x31,0xf6]
@@ -100,7 +100,7 @@ define dso_local void @test1(ptr%buf) nounwind {
100100
; EGPR-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x9c,0x04,0xd0,0x0b,0x00,0x00]
101101
; EGPR-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
102102
; EGPR-NEXT: callq foo # encoding: [0xe8,A,A,A,A]
103-
; EGPR-NEXT: # fixup A - offset: 1, value: foo-4, kind: reloc_branch_4byte_pcrel
103+
; EGPR-NEXT: # fixup A - offset: 1, value: foo, kind: reloc_branch_4byte_pcrel
104104
; EGPR-NEXT: ldtilecfg {{[0-9]+}}(%rsp) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x49,0x84,0x24,0xc0,0x03,0x00,0x00]
105105
; EGPR-NEXT: movabsq $64, %rax # encoding: [0x48,0xb8,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
106106
; EGPR-NEXT: tileloadd 3024(%rsp,%rax), %tmm3 # 1024-byte Folded Reload
@@ -116,7 +116,7 @@ define dso_local void @test1(ptr%buf) nounwind {
116116
; EGPR-NEXT: incl %r14d # encoding: [0x41,0xff,0xc6]
117117
; EGPR-NEXT: cmpw $100, %r14w # encoding: [0x66,0x41,0x83,0xfe,0x64]
118118
; EGPR-NEXT: jl .LBB0_2 # encoding: [0x7c,A]
119-
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB0_2-1, kind: FK_PCRel_1
119+
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB0_2, kind: FK_PCRel_1
120120
; EGPR-NEXT: .LBB0_3: # %exit
121121
; EGPR-NEXT: addq $4056, %rsp # encoding: [0x48,0x81,0xc4,0xd8,0x0f,0x00,0x00]
122122
; EGPR-NEXT: # imm = 0xFD8
@@ -226,7 +226,7 @@ define dso_local void @test2(ptr%buf) nounwind {
226226
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
227227
; EGPR-NEXT: testb %al, %al # encoding: [0x84,0xc0]
228228
; EGPR-NEXT: jne .LBB1_3 # encoding: [0x75,A]
229-
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB1_3-1, kind: FK_PCRel_1
229+
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB1_3, kind: FK_PCRel_1
230230
; EGPR-NEXT: # %bb.1: # %loop.header.preheader
231231
; EGPR-NEXT: movq %rdi, %rbx # encoding: [0x48,0x89,0xfb]
232232
; EGPR-NEXT: xorl %r14d, %r14d # encoding: [0x45,0x31,0xf6]
@@ -237,7 +237,7 @@ define dso_local void @test2(ptr%buf) nounwind {
237237
; EGPR-NEXT: tilezero %tmm0 # encoding: [0xc4,0xe2,0x7b,0x49,0xc0]
238238
; EGPR-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
239239
; EGPR-NEXT: callq foo # encoding: [0xe8,A,A,A,A]
240-
; EGPR-NEXT: # fixup A - offset: 1, value: foo-4, kind: reloc_branch_4byte_pcrel
240+
; EGPR-NEXT: # fixup A - offset: 1, value: foo, kind: reloc_branch_4byte_pcrel
241241
; EGPR-NEXT: ldtilecfg {{[0-9]+}}(%rsp) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x49,0x44,0x24,0x08]
242242
; EGPR-NEXT: tilezero %tmm2 # encoding: [0xc4,0xe2,0x7b,0x49,0xd0]
243243
; EGPR-NEXT: tileloadd (%rbx,%r15), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xa2,0x7b,0x4b,0x04,0x3b]
@@ -247,7 +247,7 @@ define dso_local void @test2(ptr%buf) nounwind {
247247
; EGPR-NEXT: incl %r14d # encoding: [0x41,0xff,0xc6]
248248
; EGPR-NEXT: cmpw $100, %r14w # encoding: [0x66,0x41,0x83,0xfe,0x64]
249249
; EGPR-NEXT: jl .LBB1_2 # encoding: [0x7c,A]
250-
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1
250+
; EGPR-NEXT: # fixup A - offset: 1, value: .LBB1_2, kind: FK_PCRel_1
251251
; EGPR-NEXT: .LBB1_3: # %exit
252252
; EGPR-NEXT: addq $72, %rsp # encoding: [0x48,0x83,0xc4,0x48]
253253
; EGPR-NEXT: popq %rbx # encoding: [0x5b]

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