Swap the order so comment makes more sense

Signed-off-by: Mikhail R. Gadelha <[email protected]>

Author: mikhailramalho

llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td

@@ -63,10 +63,11 @@ def : WriteRes<WriteShiftReg32, [SMX60_IEU]>;
 def : WriteRes<WriteShiftReg, [SMX60_IEU]>;
 
 // Integer multiplication
-// The latency of mul is 5, while mulh, mulhsu, mulhu is 6.
+def : WriteRes<WriteIMul32, [SMX60_IEU]>  { let Latency = 3; }
+
+// The latency of mul is 5, while in mulh, mulhsu, mulhu is 6
 // Worst case latency is used
 def : WriteRes<WriteIMul, [SMX60_IEU]>  { let Latency = 6; }
-def : WriteRes<WriteIMul32, [SMX60_IEU]>  { let Latency = 3; }
 
 // Integer division/remainder
 let Latency = 3, ReleaseAtCycles = [3] in {