Make flags register explicit.

Author: rj-jesus

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -26592,13 +26592,13 @@ performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
     SDValue TVal = Src.getOperand(0);
     SDValue FVal = Src.getOperand(1);
 
-    // SIGN_EXTEND_INREG (CSEL 0, 1, cc), i1 --> CSEL 0, -1, cc
+    // SIGN_EXTEND_INREG (CSEL 0, 1, cc, NZCV), i1 --> CSEL 0, -1, cc, NZCV
     if (isNullConstant(TVal) && isOneConstant(FVal))
       return DAG.getNode(AArch64ISD::CSEL, DL, VT, TVal,
                          DAG.getAllOnesConstant(DL, VT), Src.getOperand(2),
                          Src.getOperand(3));
 
-    // SIGN_EXTEND_INREG (CSEL 1, 0, cc), i1 --> CSEL -1, 0, cc
+    // SIGN_EXTEND_INREG (CSEL 1, 0, cc, NZCV), i1 --> CSEL -1, 0, cc, NZCV
     if (isOneConstant(TVal) && isNullConstant(FVal))
       return DAG.getNode(AArch64ISD::CSEL, DL, VT,
                          DAG.getAllOnesConstant(DL, VT), FVal,